Design of disturbance observer based on adaptive-neural control for large-scale time-delay systems in the presence of actuator fault and unknown dead zone

This article presents an adaptive neural compensation scheme for a class of large-scale time delay nonlinear systems in the presence of unknown dead zone, external disturbances, and actuator faults. In this article, the quadratic Lyapunov–Krasovskii functionals are introduced to tackle the system delays. The unknown functions of the system are estimated by using radial basis function neural networks. Furthermore, a disturbance observer is developed to approximate the external disturbances. The proposed adaptive neural compensation control method is constructed by utilizing a backstepping technique. The boundedness of all the closed-loop signals is guaranteed via Lyapunov analysis and the tracking errors are proved to converge to a small neighborhood of the origin. Simulation results are provided to illustrate the effectiveness of the proposed control approach.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

鄂尔多斯盆地榆林－神木地区上古生界裂缝和断层分布及其对天然气富集区的影响

鄂尔多斯盆地东部榆林-神木地区上古生界发育了断层和3种类型的裂缝.裂缝类型有区域构造缝、水平缝（包括层理缝与缝合线）和成岩缝,其中,区域构造缝主要呈北东向分布,在上古生界各层位均发育,缝合线在山2段中下部和太原组灰岩中都可见到,层理缝仅见于山西组山2段中下部,成岩缝仅见于石千峰组千5段.断层为逆断层,断穿了上古生界下部气藏的区域盖层和烃源岩.裂缝和断层分布对研究区重点勘探层位山2段、盒8段和千5段的天然气富集起到了重要作用：伴生的层理缝和缝合线的分布控制了山2段天然气富集区;区域构造缝的分布促进了盒8段天然气的富集;而千5段天然气的富集则依赖于本区断穿上石盒子组的断层和区域构造缝的分布.图6表2参29     

新型低压抽屉式开关柜在冶金系统的应用

介绍新型低压抽屉式开关柜的结构性能和特点，并与早期低压柜作了比较。阐述了新型低压抽屉式开关柜在冶金系统应用中的几点改进情况。     

SMT测试技术

主要介绍了当前用于检测组装后PCB的缺陷和故障的一些常见测试技术 ,并对未来的发展趋势进行了初步探讨     

Highly oriented star-like patterns observed on GaSe epilayers grown on Si(111)

Epitaxial lamellar gallium selenide (GaSe) semiconductors have been grown on trench-patterned silicon (Si) substrates by molecular beam epitaxy. An intriguing star-like patterned morphology was identified by atomic force microscopy on these epilayers. This non-trivial feature can be correlated with the accumulation of stacking faults of two concurrent epitaxial domains around self-oriented triangular pits developed earlier on the Si(111) surface by the chemical etching. Crystallographic considerations show how the stars can be formed.     

超薄SiO2层的热生长

隧道小孔中超薄ＳｉＯ２的生长是ＥＥＰＲＯＭ电路制造的关键工艺之一。采用ＳＵＰＲＥＭ－Ⅲ工艺模拟程序对超薄ＳｉＯ２的热生长进行了工艺模拟，经过大量的工艺实验及优化，确定了超薄ＳｉＯ２的最佳生长条件，生长出的ＳｉＯ２性能良好，完全可满足ＥＥＰＲＯＭ研制的要求。     

基于i860的存储器子系统设计

微处理机系统中的存储器子系统设计对整个系统性能的高低有重要的影响，尤其当微处理器的主频越来越高时。本文结合实际例子，给出了一个基于ｉ８６０处理器（４０ＭＨｚ）的主存设计方案，讨论了实际中需仔细考虑的因素。该设计可为其它高性能ＲＩＳＣ系统设计提供参考。     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.