Fault-aware Communication Mapping for NoCs with Guaranteed Latency

As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival probability and response time. We address the problem of transient link failures by means of temporally and spatially redundant transmission of messages, such that designer-imposed message arrival probabilities are guaranteed. Response time minimisation is achieved by a heuristic that statically assigns multiple copies of each message to network links, intelligently combining temporal and spatial redundancy. Concerns regarding energy consumption are addressed in two ways. First, we reduce the total amount of transmitted messages, and, second, we minimise the application response time such that the resulted time slack can be exploited for energy savings through voltage reduction. The advantages of the proposed approach are guaranteed message arrival probability and guaranteed worst case application response time.     

Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip

Network-on-chip-based multiprocessor systems-on-chip are considered as future embedded systems platforms. One of the steps in mapping an application onto such a parallel platform involves scheduling the communication on the network-on-chip. This paper presents different scheduling strategies that minimize resource usage by exploiting all scheduling freedom offered by networks-on-chip. It also introduces a technique to take the dynamism in applications into account when scheduling the communication of an application on the network-on-chip while minimizing the resource usage. Our experiments show that resource-utilization is improved when compared to existing techniques.     

Analysis of worst-case backlog bounds for Networks-on-Chip

In networks-on-chips (NoCs), analyzing the worst-case backlog bounds of routers is very important to identify network congestions and improve network performance. In this paper, we propose a method called DiGB (DIrected-contention-Graph-based Backlog bound derivation) to analyze worst-case backlog bounds. For primitive scenarios, we propose analytical models for backlog bound derivation. For complex scenarios, we first construct a directed-contention-graph (DCG) to analyze the relationships among traffic flows. Then, we use the Breadth-First-Search strategy to traverse the DCG so that complex scenarios can be divided into primitive scenarios. Finally we compute the worst-case backlog bounds of each router. To illustrate this method, we present the derivation of closed-form formulas to compute the worst-case backlog bounds under all-to-one gather communication. The experimental results show that our method can achieve correct and tight worst-case backlog bounds.     

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs

As one of the main trends of communication technology for 3D integrated circuits, the 3D networks-on-chip (NoCs) have drawn high concern from the academia. The links are main components of the NoCs. For the permanent link faults, the fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of the 2D NoCs. In this paper, we propose a low-overhead fault-tolerant routing scheme called LOFT for 3D Mesh NoCs without requiring any virtual channels (VCs). LOFT is a deadlock-free scheme by adopting a logic-based routing named LBDRe² guided by a turn model Complete-OE. The experimental results show that LOFT possesses better performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing schemes.     

Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications

In the near future, small electronic hand-held devices will be equipped with digital cameras capable of acquiring high resolution images (HDTV) at real-time rates, resulting in video streams of dozens of megabytes per second. The real-time video decoding and especially encoding of such streams with AVC/ H.264 or SVC standards require a huge amount of computing power that, in the case of a hand-held device, has to be delivered under the constraint of low power dissipation. In this paper we present a Multi-Processor System-on-Chip dedicated for high performance, low-power video coding applications using Network-on-Chip (NoC) as communication infrastructure. Extensive experiments have established the power dissipation models of individual NoC components, i.e. network interfaces, routers and wires. Based on these models and the NoC topology, we build the power model of the complete NoC. For three different implementation scenarios of the AVC/H.264 simple profile encoder we derive the power dissipation of the NoC for image resolutions up to HDTV at rate of 30 frames per second. The results obtained show that for the same application mapping scenario (worst case), moving from CIF to HDTV resolution will result in a 35% increase of the total power dissipation. Finally, for HDTV resolution, the difference in power dissipation between the worst (21 mW) and the best case application mapping scenario is 26%.

基于片上网络的并行计算技术研究

片上网络（Networks—on—chip,NoC）作为当今微电子学研究的热门方向之一,受到了越来越多的关注。本文将并行计算技术应用到片上网络中,通过并行编程实现处理器并行计算以及相互间的通信。     

Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach

In the era of many-core chips, the problem of power density is a serious challenge. This is particularly important in Network-on-Chip (NoC)-based systems, where application mapping determines the resulting power patterns and the workload distribution across the entire chip. Despite this fact, the majority of mapping algorithms focus on performance, and the resulting power patterns are largely ignored. This work investigates this problem. Three different power pattern metrics with different scopes are defined, namely, power peak, power range, and regional power density. The results of using them as mapping objectives together with communication cost using a multi-objective evolutionary mapping approach are investigated. Results show that employing power patterns results-in Pareto fronts with different power patterns and features. Results are analysed and discussed. Moreover, a case study of thermal analysis of the resulting power patterns is performed. Results show that using communication cost only results-in large hotspots which translates into higher peak and range of chip temperatures. The proposed mapping objectives are shown to significantly improve thermal balancing (up to 55%) and peak temperature (up to 7.77%). These results indicate the importance of considering power patterns in the design of NoC-based many-core systems and their direct impact on the reliability and performance of such systems.     

A NoC-based hybrid message-passing/shared-memory approach to CMP design

Future chip-multiprocessors (CMP) will integrate many cores interconnected with a high-bandwidth and low-latency scalable network-on-chip (NoC). However, the potential that this approach offers at the transport level needs to be paired with an analogous paradigm shift at the higher levels. In particular, the standard shared-memory programming model fails to address the requirements of scalability of the many-core era. Fast data exchange among the cores and low-latency synchronization are desirable but hard to achieve in practice due to the memory hierarchy. The message-passing paradigm permits instead direct data communication and synchronization between the cores. The shared-memory could still be used for the instruction fetch. Hence, we propose a hybrid approach that combines shared-memory and message passing in a single general-purpose CMP architecture that allows efficient execution of applications developed with both parallel programming approaches. Cores fetch instructions from a hierarchical memory and exchange their data through the same memory, for compatibility with existing software, or directly through the fast NoC. We developed a fast SystemC based cycle-accurate simulator for design space explorations that we used to evaluate the performance with real benchmarks. The various components have been RTL coded and mapped to a CMOS 45 nm technology to build a silicon area model that we used to select the best architectural configurations.     

A hardwired NoC infrastructure for embedded systems on FPGAs

A hardwired network-on-chip based on a modified Fat Tree (MFT) topology is proposed as a communication infrastructure for future FPGAs. With extremely simple routing, such an infra structure would greatly enhance the ongoing trend of embedded systems implementation using multi-cores on FPGAs. An efficient H-tree based floor plan that naturally follows the MFT construction methodology was developed. Several instances of the proposed NoC were implemented with various inter-routers links progression schemes combined with very simple router architecture and efficient client network interface (CNI). The performance of all these implementations was evaluated using a cycle-accurate simulator for various combinations of NoC sizes and traffic models. Also a new data transfer circuit for transferring data between clients and NoC operating at different (unrelated) clock frequencies has been developed. Allowing data transfer at one data per cycle, the operation of this circuit has been verified using gate-level simulations for several ratios of NoC/client clock frequencies.