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1.
2.
Chaos optimization algorithm (COA) utilizes the chaotic maps to generate the pseudo-random sequences mapped as the decision variables for global optimization applications. A kind of parallel chaos optimization algorithm (PCOA) has been proposed in our former studies to improve COA. The salient feature of PCOA lies in its pseudo-parallel mechanism. However, all individuals in the PCOA search independently without utilizing the fitness and diversity information of the population. In view of the limitation of PCOA, a novel PCOA with migration and merging operation (denoted as MMO-PCOA) is proposed in this paper. Specifically, parallel individuals are randomly selected to be conducted migration and merging operation with the so far parallel solutions. Both migration and merging operation exchange information within population and produce new candidate individuals, which are different from those generated by stochastic chaotic sequences. Consequently, a good balance between exploration and exploitation can be achieved in the MMO-PCOA. The impacts of different one-dimensional maps and parallel numbers on the MMO-PCOA are also discussed. Benchmark functions and parameter identification problems are used to test the performance of the MMO-PCOA. Simulation results, compared with other optimization algorithms, show the superiority of the proposed MMO-PCOA algorithm. 相似文献
3.
This paper discusses the capability of Guo et al.'s (2021) equations to determine the discharge of radial gates under submerged flow conditions. It was concluded that Guo et al.'s (2021) equations are associated with error reduction compared to the Incomplete Self-Similarity (ISS) theory and the calibration method. However, it does not have a significant advantage over Energy-Momentum (E-M) approach. Employing E-M principles, new equations were proposed to determine the discharge of radial gates, which has some advantages compared to Guo et al. (2021), such as (1) error reduction under partially and fully submerged flow conditions, (2) least dependence on the empirical constants, (3) uniformity of form over the entire submerged condition, and (4) no need to classify the submerged flow. Field calibration showed that the proposed equations in the present study for a single gate predict the discharge of parallel radial gates with a mean absolute error of less than 4.5% subject to the submerged operation of all open gates. 相似文献
4.
Crashworthiness simulation system is one of the key computer-aided engineering (CAE) tools for the automobile industry and implies two potential conflicting requirements: accuracy and efficiency. A parallel crashworthiness simulation system based on graphics processing unit (GPU) architecture and the explicit finite element (FE) method is developed in this work. Implementation details with compute unified device architecture (CUDA) are considered. The entire parallel simulation system involves a parallel hierarchy-territory contact-searching algorithm (HITA) and a parallel penalty contact force calculation algorithm. Three basic GPU-based parallel strategies are suggested to meet the natural parallelism of the explicit FE algorithm. Two free GPU-based numerical calculation libraries, cuBLAS and Thrust, are introduced to decrease the difficulty of programming. Furthermore, a mixed array and a thread map to element strategy are proposed to improve the performance of the test pairs searching. The outer loop of the nested loop through the mixed array is unrolled to realize parallel searching. An efficient storage strategy based on data sorting is presented to realize data transfer between different hierarchies with coalesced access during the contact pairs searching. A thread map to element pattern is implemented to calculate the penetrations and the penetration forces; a double float atomic operation is used to scatter contact forces. The simulation results of the three different models based on the Intel Core i7-930 and the NVIDIA GeForce GTX 580 demonstrate the precision and efficiency of this developed parallel crashworthiness simulation system. 相似文献
5.
6.
USB数据传输中CRC校验码的并行算法实现 总被引:8,自引:2,他引:6
文章介绍了用于USB总线数据传输的CRC校验的原理和算法,并且采用并行电路实现USB2.0中的CRC产生和CRC校验,与传统的串行电路实现相比,并行电路实现方法虽然在芯片面积上大于串行电路实现,但由于降低了时钟频率,电路更容易综合实现,并且大大降低了功耗,有利于低功耗电路设计。 相似文献
7.
文章针对一维长序DFT计算问题,分析其计算结构以及算法的并行性,提出一种阵列协处理结构.并分析这种协处理机结构上DFT计算的组织及具体实施算法步骤和方法,并对这种协处理阵列结构上运行的DFT进行复杂性分析。这对计算DFT专用集成协处理结构芯片开发,提高专用嵌套系统性能非常实用。 相似文献
8.
A transformational approach for proving termination of parallel logic programs such as GHC programs is proposed. A transformation
from GHC programs to term rewriting systems is developed; it exploits the fact that unifications in GHC-resolution correspond
to matchings. The termination of a GHC program for a class of queries is implied by the termination of the resulting rewrite
system. This approach facilitates the applicability of a wide range of termination techniques developed for rewrite systems
in proving termination of GHC programs. The method consists of three steps: (a) deriving moding information from a given GHC
program, (b) transforming the GHC program into a term rewriting system using the moding information, and finally (c) proving
termination of the resulting rewrite system. Using this method, the termination of many benchmark GHC programs such as quick-sort,
merge-sort, merge, split, fair-split and append, etc., can be proved.
This is a revised and extended version of Ref. 12). The work was partially supported by the NSF Indo-US grant INT-9416687
Kapur was partially supported by NSF Grant nos. CCR-8906678 and INT-9014074.
M. R. K. Krishna Rao, Ph.D.: He currently works as a senior research fellow at Griffith University, Brisbane, Australia. His current interests are in
the areas of logic programming, modular aspects and noncopying implementations of term rewriting, learning logic programs
from examples and conuterexamples and dynamics of mental states in rational agent architectures. He received his Ph.D in computer
science from Tata Institute of Fundamental Research (TIFR), Bombay in 1993 and worked at TIFR and Max Planck Institut für
Informatik, Saarbrücken until January 1997.
Deepak Kapur, Ph.D.: He currently works as a professor at the State University of New York at Albany. His research interests are in the areas
of automated reasoning, term rewriting, constraint solving, algebraic and geometric reasoning and its applications in computer
vision, symbolic computation, formal methods, specification and verification. He obtained his Ph.D. in Computer Science from
MIT in 1980. He worked at General Electric Corporate Research and Development until 1987. Prof. Kapur is the editor-in-chief
of the Journal of Automated Reasoning. He also serves on the editorial boards of Journal of Logic Programming, Journal on
Constraints, and Journal of Applicable Algebra in Engineering, Communication and Computer Science.
R. K. Shyamasundar, Ph.D.: He currently works as a professor at Tata Institute of Fundamental Research (TIFR), Bombay. His current intersts are in
the areas of logic programming, reactive and real time programming, constraint solving, formal methods, specification and
verification. He received his Ph.D in computer science from Indian Institute of Science, Bangalore in 1975 and has been a
faculty member at Tata Institute of Fundamental Research since then. He has been a visiting/regular faculty member at Technological
University of Eindhoven, University of Utrecht, IBM TJ Watson Research Centre, Pennsylvania State University, University of
Illinois at Urbana-Champaign, INRIA and ENSMP, France. He has served on (and chaired) Program Committees of many International
Conferences and has been on the Editorial Committees. 相似文献
9.
In this paper,a sequential algorithm computing the aww vertex pair distance matrix D and the path matrix Pis given.On a PRAM EREW model with p,1≤p≤n^2,processors,a parallel version of the sequential algorithm is shown.This method can also be used to get a parallel algorithm to compute transitive closure array A^* of an undirected graph.The time complexity of the parallel algorithm is O(n^3/p).If D,P and A^* are known,it is shown that the problems to find all connected components,to compute the diameter of an undirected graph,to determine the center of a directed graph and to search for a directed cycle with the minimum(maximum)length in a directed graph can all be solved in O(n^2/p logp)time. 相似文献
10.
并行哈夫曼编码器的硬件设计与实现 总被引:5,自引:4,他引:1
文章设计了一种并行编码的哈夫曼硬件编码器,它采用了流水线和并行编码方法,使得在一个时钟周期内可以编码一个字节的数据,在编码时显著降低了工作频率。文章给出了关键部分的实现方案并分析了实验结果。 相似文献