A RISC architecture extended by an efficient tightly coupled reconfigurable unit

In this paper, the architecture of an embedded processor extended with a tightly-coupled coarse-grain reconfigurable functional unit (RFU) is proposed. The efficient integration of the RFU with the control unit and the datapath of the processor eliminate the communication overhead between them. To speed up execution, the RFU exploits instruction level parallelism (ILP) and spatial computation. Also, the proposed integration of the RFU efficiently exploits the pipeline structure of the processor, leading to further performance improvements. Furthermore, a development framework for the introduced architecture is presented. The framework is fully automated, hiding all reconfigurable hardware related issues from the user. The hardware model of the architecture was synthesized in a 0.13?µm process and all information regarding area and delay were estimated and presented. A set of benchmarks is used to evaluate the architecture and the development framework. Experimental results prove performance improvements in addition to potential energy reduction.     

基于改进遗传与模拟退火融合的RISP软硬件划分

软硬件划分是可重构指令集处理器在软硬件协同设计中的关键问题,通过对比遗传算法和经典模拟退火算法的优缺点,提出改进遗传算法的适应度函数,同时将Tsallis接受准则引入到经典模拟退火当中;其思路是用遗传算法的结果来制约模拟退火算法产生的随机状态,然后由模拟退火的接受准则以及产生的随机状态函数对遗传算法的种群进行更新,从而找到全局近似最优解;实验结果证明,改进算法与单一遗传算法以及经典模拟退火算法相比,其收敛速度和适应度更好,找到全局近似最优解的概率更大。