Reconfigurable hardware implementation of a phase-correlation stereoalgorithm

This paper describes the implementation of a stereo-vision system using Field Programmable Gate Arrays (FPGAs). Reconfigurable hardware, including FPGAs, is an attractive platform for implementing vision algorithms due to its ability to exploit parallelism often found in these algorithms, and due to the speed with which applications can be developed as compared to hardware. The system outputs 8-bit, subpixel disparity estimates for 256× 360 pixel images at 30,fps. A local-weighted phase correlation algorithm for stereo disparity [Fleet, D. J.: {Int. Conf. Syst. Man Cybernetics 1:48–54 (1994)] is implemented. Despite the complexity of performing correlations on multiscale, multiorientation phase data, the system runs as much as 300 times faster in hardware than its software implementation. This paper describes the hardware platform used, the algorithm, and the issues encountered during its hardware implementation. Of particular interest is the implementation of multiscale, steerable filters, which are widely used in computer vision algorithms. Several trade-offs (reducing the number of filter orientations from three to two, using fixed-point computation, changing the location of one localized low-pass filter, and using L1 instead of L2 norms) were required to both fit the design into the available hardware and to achieve video-rate processing. Finally, results from the system are given both for synthetic data sets as well as several standard stereo-pair test images.     

A review on queueing network models with finite capacity queues for software architectures performance prediction

A review is carried out on how queueing network models with blocking have been applied so far into the performance evaluation and prediction of Software Architectures (SA). Queueing network models with finite capacity queues and blocking have recently been introduced and applied as more realistic models of systems with finite capacity resources and population constraints. Queueing network models have been often adopted as models for the evaluation of software performance. Starting from our own experience, we observe the need of a more accurate definition of the performance models of SA to capture some features of the communication systems. We consider queueing networks with finite capacity and blocking after service (BAS) to represent some synchronization constraints that cannot be easily modeled with queueing network models with infinite capacity queues. We investigate the use of queueing networks with blocking as performance models of SA with concurrent components and synchronous communication. Queueing theoretic analysis is used to solve the queueing network model and study the synchronous communication and performance of concurrent software components. Our experience is supported by other approaches that also propose the use of queueing networks with blocking. Directions for future research work in the field are included.     

A systematic approach for product families formation in Reconfigurable Manufacturing Systems

The aim of this work is to establish a methodology for an effective working of Reconfigurable Manufacturing Systems (RMSs). These systems are the next step in manufacturing, allowing the production of any quantity of highly customised and complex products together with the benefits of mass production. In RMSs, products are grouped into families, each of which requires a system configuration. The system is configured to produce the first family of products. Once it is finished, the system is reconfigured in order to produce the second family, and so forth. Therefore, the effectiveness of a RMS depends on the formation of the best set of product families. Therefore, a methodology for grouping products into families, which takes into account the requirements of products in RMSs, is an issue of core importance. These requirements are modularity, commonality, compatibility, reusability, and product demand. The methodology starts by calculating, for each product requirement, a matrix that summarises the similarity between pairs of products. Then, through the use of the AHP methodology, a unique matrix that comprises the similarity values between products is obtained. The Average Linkage Clustering algorithm is applied to this matrix in order to obtain a dendogram that shows the diverse sets of product families that may be formed.     

A reconfigurable VLSI-based double-lens tracking camera

Watching and tracking an object while seeing a much wider view is one of advantages of the eye system. We proposed and developed a tracking camera system that mimics the eyes by using double-lens modules. In the system, a wide view is captured through the wide-lens module, while the target in it is tracked and magnified through the telescopic lens module. Electronic circuits for tracking control are implemented onto the reconfigurable VLSI or FPGA in order to embed the parallelism in the tracking algorithm into the hardware. A successfully developed FPGA-based prototype performs high-speed tracking at the video-rate. This work was present in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27, 2007     

Fast finite difference Poisson solvers on heterogeneous architectures

In this paper we propose and evaluate a set of new strategies for the solution of three dimensional separable elliptic problems on CPU–GPU platforms. The numerical solution of the system of linear equations arising when discretizing those operators often represents the most time consuming part of larger simulation codes tackling a variety of physical situations. Incompressible fluid flows, electromagnetic problems, heat transfer and solid mechanic simulations are just a few examples of application areas that require efficient solution strategies for this class of problems. GPU computing has emerged as an attractive alternative to conventional CPUs for many scientific applications. High speedups over CPU implementations have been reported and this trend is expected to continue in the future with improved programming support and tighter CPU–GPU integration. These speedups by no means imply that CPU performance is no longer critical. The conventional CPU-control–GPU-compute pattern used in many applications wastes much of CPU’s computational power. Our proposed parallel implementation of a classical cyclic reduction algorithm to tackle the large linear systems arising from the discretized form of the elliptic problem at hand, schedules computing on both the GPU and the CPUs in a cooperative way. The experimental result demonstrates the effectiveness of this approach.     

自适应二进制算术编码的动态可重构实现研究

针对H.266/VVC视频编码标准下的上下文自适应二进制算术编码器编码速度慢、资源开销大的问题,面向可重构结构依据算法的内在并行特性优化了编码架构,并基于动态可重构阵列处理器设计实现了CABAC编码器常规编码模式下的并行映射方法,阵列结构能够根据编码输入对优化后的算法进行动态重构,在避免专用硬件编码器较高的资源开销情况下利用软件重构的方法实现熵编码过程,保证编码准确性的同时提高了视频数据流编码效率,为此类运算密集型算法的硬件实现提供了更为灵活高效的参考途径。仿真结果表明,映射实现的编码过程中每个编码周期完成5个二进制序列的编码,平均编码效率达到384.13Mbin/s。基于FPGA的测试结果表明,软件重构方法与专用硬件实现的编码器相比,资源开销降低且编码效率提升5.47%,与同类型可重构视频编码结构相比,编码效率提升7.03%。     

Semantic-based QoS management in cloud systems: Current status and future challenges

Cloud Computing and Service Oriented Architectures have seen a dramatic increase of the amount of applications, services, management platforms, data, etc. gaining momentum for the necessity of new complex methods and techniques to deal with the vast heterogeneity of data sources or services. In this sense Quality of Service (QoS) seeks for providing an intelligent environment of self-management components based on domain knowledge in which cloud components can be optimized easing the transition to an advanced governance environment. On the other hand, semantics and ontologies have emerged to afford a common and standard data model that eases the interoperability, integration and monitoring of knowledge-based systems. Taking into account the necessity of an interoperable and intelligent system to manage QoS in cloud-based systems and the emerging application of semantics in different domains, this paper reviews the main approaches for semantic-based QoS management as well as the principal methods, techniques and standards for processing and exploiting diverse data providing advanced real-time monitoring services. A semantic-based framework for QoS management is also outlined taking advantage of semantic technologies and distributed datastream processing techniques. Finally a discussion of existing efforts and challenges is also provided to suggest future directions.     

Performance analysis challenges and framework for high-performance reconfigurable computing

Reconfigurable computing (RC) applications employing both microprocessors and FPGAs have potential for large speedup when compared with traditional (software) parallel applications. However, this potential is marred by the additional complexity of these dual-paradigm systems, making it difficult to identify performance bottlenecks and achieve desired performance. Performance analysis concepts and tools are well researched and widely available for traditional parallel applications but are lacking in RC, despite being of great importance due to the applications’ increased complexity. In this paper, we explore challenges and present new techniques in automated instrumentation, runtime measurement, and visualization of RC application behavior. We also present ideas for integration with conventional performance analysis tools to create a unified tool for RC applications as well as our initial framework for FPGA instrumentation and measurement. Results from a case study are provided using a prototype of this new tool.