Multi-resource scheduling for FPGA systems

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.     

Reconfigurable hardware implementation of a phase-correlation stereoalgorithm

This paper describes the implementation of a stereo-vision system using Field Programmable Gate Arrays (FPGAs). Reconfigurable hardware, including FPGAs, is an attractive platform for implementing vision algorithms due to its ability to exploit parallelism often found in these algorithms, and due to the speed with which applications can be developed as compared to hardware. The system outputs 8-bit, subpixel disparity estimates for 256× 360 pixel images at 30,fps. A local-weighted phase correlation algorithm for stereo disparity [Fleet, D. J.: {Int. Conf. Syst. Man Cybernetics 1:48–54 (1994)] is implemented. Despite the complexity of performing correlations on multiscale, multiorientation phase data, the system runs as much as 300 times faster in hardware than its software implementation. This paper describes the hardware platform used, the algorithm, and the issues encountered during its hardware implementation. Of particular interest is the implementation of multiscale, steerable filters, which are widely used in computer vision algorithms. Several trade-offs (reducing the number of filter orientations from three to two, using fixed-point computation, changing the location of one localized low-pass filter, and using L1 instead of L2 norms) were required to both fit the design into the available hardware and to achieve video-rate processing. Finally, results from the system are given both for synthetic data sets as well as several standard stereo-pair test images.     

A systematic approach for product families formation in Reconfigurable Manufacturing Systems

The aim of this work is to establish a methodology for an effective working of Reconfigurable Manufacturing Systems (RMSs). These systems are the next step in manufacturing, allowing the production of any quantity of highly customised and complex products together with the benefits of mass production. In RMSs, products are grouped into families, each of which requires a system configuration. The system is configured to produce the first family of products. Once it is finished, the system is reconfigured in order to produce the second family, and so forth. Therefore, the effectiveness of a RMS depends on the formation of the best set of product families. Therefore, a methodology for grouping products into families, which takes into account the requirements of products in RMSs, is an issue of core importance. These requirements are modularity, commonality, compatibility, reusability, and product demand. The methodology starts by calculating, for each product requirement, a matrix that summarises the similarity between pairs of products. Then, through the use of the AHP methodology, a unique matrix that comprises the similarity values between products is obtained. The Average Linkage Clustering algorithm is applied to this matrix in order to obtain a dendogram that shows the diverse sets of product families that may be formed.     

A reconfigurable VLSI-based double-lens tracking camera

Watching and tracking an object while seeing a much wider view is one of advantages of the eye system. We proposed and developed a tracking camera system that mimics the eyes by using double-lens modules. In the system, a wide view is captured through the wide-lens module, while the target in it is tracked and magnified through the telescopic lens module. Electronic circuits for tracking control are implemented onto the reconfigurable VLSI or FPGA in order to embed the parallelism in the tracking algorithm into the hardware. A successfully developed FPGA-based prototype performs high-speed tracking at the video-rate. This work was present in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27, 2007     

Run-time generation of partial FPGA configurations

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.     

自适应二进制算术编码的动态可重构实现研究

针对H.266/VVC视频编码标准下的上下文自适应二进制算术编码器编码速度慢、资源开销大的问题,面向可重构结构依据算法的内在并行特性优化了编码架构,并基于动态可重构阵列处理器设计实现了CABAC编码器常规编码模式下的并行映射方法,阵列结构能够根据编码输入对优化后的算法进行动态重构,在避免专用硬件编码器较高的资源开销情况下利用软件重构的方法实现熵编码过程,保证编码准确性的同时提高了视频数据流编码效率,为此类运算密集型算法的硬件实现提供了更为灵活高效的参考途径。仿真结果表明,映射实现的编码过程中每个编码周期完成5个二进制序列的编码,平均编码效率达到384.13Mbin/s。基于FPGA的测试结果表明,软件重构方法与专用硬件实现的编码器相比,资源开销降低且编码效率提升5.47%,与同类型可重构视频编码结构相比,编码效率提升7.03%。     

可重构阵列自主容错方法研究

设计了一种具有故障自诊断和自修复能力的可重构阵列单元结构。在功能细胞单元内部实现分布式的故障自诊断,在测试到故障后,可以自主地将距故障单元最近的空闲单元进行替换,接着自动取消受故障影响的线网,并在新的布线端点间对这些线网重新布线。以4位并行乘法器为例,实验结果证明了可重构单元阵列的故障自修复能力,并验证其重构时间较短且可靠性较高。     

面向功能进化的可重构路由器体系结构研究

由于新协议和业务的不断涌现,传统路由器的刚性和封闭性导致其无法满足上层业务发展而自由演进,因此面向功能进化的开放可重构路由器是今后发展的趋势。提出了基于积木式组装机制的可重构路由器体系结构,通过基于多矢量映射的可重构机制,利用局部矢量变化实现自身功能的不断更新、添加或删除来实现路由器功能进化,从而有力支撑上层业务的演进。     

Performance analysis challenges and framework for high-performance reconfigurable computing

Reconfigurable computing (RC) applications employing both microprocessors and FPGAs have potential for large speedup when compared with traditional (software) parallel applications. However, this potential is marred by the additional complexity of these dual-paradigm systems, making it difficult to identify performance bottlenecks and achieve desired performance. Performance analysis concepts and tools are well researched and widely available for traditional parallel applications but are lacking in RC, despite being of great importance due to the applications’ increased complexity. In this paper, we explore challenges and present new techniques in automated instrumentation, runtime measurement, and visualization of RC application behavior. We also present ideas for integration with conventional performance analysis tools to create a unified tool for RC applications as well as our initial framework for FPGA instrumentation and measurement. Results from a case study are provided using a prototype of this new tool.