对DAG-MAP算法的研究

DAG－MAP是一个面向延迟优化的FPGA工艺映射算法,其中的标记过程是该算法的核心.文章对原算法中的标记过程进行了研究,并且提出了一个改进的标记方法.通过对MCNC标准测试电路的实验结果表明该算法比原算法更为有效,并且算法所用时间没有明显的增加.     

Reducing average and peak temperatures of VLSI CMOS circuits by means of evolutionary algorithm applied to high level synthesis

In this paper an adaptive evolutionary algorithm (AEA) for high-level synthesis, resulting in reduction of the power dissipation in CMOS circuits is presented. It enables us to design contemporary electronic circuits/systems with minimisation of the peak and average power consumption, which leads to reduction of the peak and average temperature of the designed chip. Therefore, the reliability of the integrated circuit (IC) can be improved. The results of experiments carried out for the chosen benchmark circuits show that the achieved reduction of power consumption varies from 4 to 52%.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

神经网络的VLSI实现

本文评述了当前神经网络电路实现的关键技术和研究现状,着重讨论了数字、模拟和脉冲流VLSI实现的电路技术及其未来发展。     

Floating-Gate Circuits for Adaptation of Saccadic Eye Movement Accuracy

In this paper we describe an analog VLSI circuit, fabricatedusing a standard 2 µm, n-well, BiCMOS process,which utilizes floating-gate structures for non-volatile, on-chip,analog parameter storage. This circuit is designed to operatein the context of a hardware model of the primate oculomotorsystem and performs visually-guided, saccadic adaptation. Thechip contains a one-dimensional array of photoreceptors and floating-gatecircuits which are used to map retinal positions to motor outputcommands. The system's functionality is demonstrated by trainingthe chip with several different mapping functions using a supervised-learningtechnique.     

MPEG-4视频编码器象素压缩模块的VLSI结构设计

文章设计了一种基于MPEG-4的视频压缩编码器中象素压缩模块的VLSI结构。该设计采用分布算式结构——NEDA作为DCT变换的核心技术；应用基于LUT表结构使量化／反量化模块的设计简洁明了；同时对AC／DC预测模块还应用了新的存储策略，大大降低了FPGA中宝贵的存储空间。在满足处理速度和精度的要求下，利用了较少的晶体管数目和简洁的结构实现了象素压缩模块。     

基于模块化结构的N位加法器的测试生成

针对单个ｓｔｕｃｋ－ａｔ故障，研究了Ｎ位加法器的测试矢量生成问题，对于行波进位加法器，只需８个测试矢量就可得到１００％的故障覆盖率；对于Ｎ位先行进位加法器，只需Ｎ＾２＋２Ｎ＋３个测试矢量即可得到１００％的故障覆盖率。     

一种AMR语音编码器的VLSI设计及FPGA实现

AMR(自适应多速率)语音编码标准由于其低码率和高质量,在通信和多媒体领域得到广泛应用.针对AMR语音编码标准的算法特点,提出了一种"音频DSP软核+硬件加速器"的VLSI实现结构.这种结构能够有效地实现编码算法,同时达到低成本、低功耗的要求.综合后的电路在满足语音编码实时性的要求下能工作在50MHz频率以下,功耗仅有不到50mW,和78 k门的芯片面积.最后通过FPGA整体验证,证明这种方案是可行有效的.同时优化后的音频DSP软核和硬件加速器中的模块复用设计,使得本设计方案对G.7xx系列编码算法具有通用和可移植性.     

Design and VLSI evaluation of a high-speed cellular array divider with a selection function

In recent years, very fast dividers have been required for the real-time application of digital signal processing, robot control, and the like. This paper proposes a high-speed cellular array divider with a selection function that is based on the non-restoring algorithm and can deal with both fixed-point and negative operands in two's complement form. This divider uses new techniques that can generate in parallel both the quotient bit of one row and a partial remainder and CLS bit of the next row. The delay time of the proposed divider is calculated in terms of a delay of one unit such as a NAND gate. Finally, by using PARTHENON, a CAD (computer-aided design) system for VLSI, this divider is designed and evaluated. As a result, elimination of the delay time for even rows becomes possible. Thus, the delay time can be decreased to approximately one half that of the high-speed divider proposed by Cappa and Hamacher, which uses the most general high-speed techniques of carry-save and CLA.     

Estimating optical flow with cellular neural networks

The cellular neural network is a locally interconnected neural network capable of high-speed computation when implemented in analog VLSI. This work describes a CNN algorithm for estimating the optical flow from an image sequence. The algorithm is based on the spatio-temporal filtering approach to image motion analysis and is shown to estimate the optical flow more accurately than a comparable approach proposed previously. Two innovative features of the algorithm are the exploitation of a biological model for hyperacuity and the development of a new class of spatio-temporal filter better suited for image motion analysis than the commonly used space–time Gabor filter. © 1998 John Wiley & Sons, Ltd.