Extending SSD Lifespan with Comprehensive Non-Volatile Memory-Based Write Buffers

Journal of Computer Science and Technology - New non-volatile memory (NVM) technologies are expected to replace main memory DRAM (dynamic random access memory) in the near future. NAND flash...     

一种低功耗Cache设计技术的研究

低功耗、高性能的cache系统设计是嵌入式DSP芯片设计的关键。本文在多媒体处理DSP芯片MD32的设计实践中，提出一种利用读／写缓冲器作为零级cache，减少对数据、指令cache的读／写次数，由于缓冲器读取功耗远远小于片上cache，从而减小cache相关功耗的方法。通过多种多媒体处理测试程序的验证，该技术可减少对指令cache或者数据cache20％～40％的读取次数，以较小芯片面积的增加换取了较大的功耗降低。     

An accurate and practical buffer allocation model for the buffer cache based on marginal gains

A new dynamic buffer allocation strategy based on the notion of marginal gains is presented for the buffer cache that is used by the operating system to store frequently accessed disk blocks in main memory, and the performance of the proposed strategy is compared with those of previous allocation strategies. In the proposed strategy, marginal gain values are predicted by exploiting functions that approximate the expected number of buffer hits per unit time. Experimental results from both trace-driven simulation and an actual implementation in the FreeBSD operating system show that the proposed strategy accurately predicts the marginal gain values for various workloads resulting in significantly improved buffer hit ratios.     

Experience with Applying Formal Methods to Protocol Specification and System Architecture

In the last three years or so we at Enterprise Platforms Group at Intel Corporation have been applying formal methods to various problems that arose during the process of defining platform architectures for Intel's processor families. In this paper we give an overview of some of the problems we have worked on, the results we have obtained, and the lessons we have learned. The last topic is addressed mainly from the perspective of platform architects.     

软件定义车联网中缓存辅助的NOMA功率分配方案研究

由于对丰富多媒体服务的需求日益增长,车联网需要提供海量的设备连接以满足高频谱效率和低延迟的需求。软件定义网络（SDN）、缓存和非正交多址接入（NOMA）被认为是有效解决这些关键挑战的潜在技术。针对软件定义车联网,提出了一种缓存辅助的NOMA功率分配方案。首先,针对车联网中车辆总是处于高速运动状态的特点,提出了一种新的簇头选择算法,到达的道路交通将借助SDN进行预测,实现自适应车辆分簇。其次,引入了缓存辅助的NOMA方案,每个车辆在文件缓存阶段使用NOMA原理缓存和请求文件。再次,针对双Nakagami-m衰落条件下的两个簇头车辆通信场景,提出了一种最优功率分配策略,将优化问题公式化为找到每辆车的最佳功率曲线,从而最大化地在每辆车上成功解码目标文件的概率。最后,数值仿真和理论分析表明,所提缓存辅助NOMA功率分配方案,性能明显优于传统的NOMA和缓存辅助的OMA。     

一种空间信息网络缓存决策策略

针对空间信息网络（space information network,SIN）中卫星节点缓存容量有限,且卫星高速移动使得星间链路时变,导致地面用户内容访问延迟增大的问题,提出一种基于人工蜂群算法的空间信息网络缓存决策策略（satellite improved artificial bee colony,SIABC）。首先根据低轨卫星节点链路切换的周期性和可预知性,建立网络分区模型,对空间信息网络的卫星节点进行分区,在此基础上,建立区域节点协作缓存模型,使得整个网络区域内的卫星节点有选择性地缓存不同流行度的内容,同时兼顾区域内节点的协作缓存,从而流行度高的内容缓存在网络边缘。仿真结果表明,与现有缓存机制相比,该缓存策略能够明显提高内容的平均缓存命中率,并显著降低用户的内容访问时延。     

基于预测与优先级缓存的MIPv6切换算法

为了提升移动IPv6的切换性能,保证实时性要求高的音频、视频等业务的服务质量,针对去除DAD过程的RDMIPv6方案未考虑在传输速率相对较慢的无线信道中,移动节点向NAR本地注册所产生的时延以及切换过程中引入的丢包问题,提出一种优化方案PCRD-MIPv6。PCRD-MIPv6方案结合基于L2触发的切换预测和数据包优先级缓存机制,在L2切换完成之前向移动节点MN维护的接入路由器缓存列表T_AR中的所有AR发送MOA实现本地注册,与此同时,将切换过程中的数据包按优先级缓存在PAR中,在切换完成后发往移动节点,从而减少切换过程中的丢包率。NS-2仿真结果表明,PCRD-MIPv6方案有效地减少了切换时延,降低了切换过程中的丢包率。     

软件定义网络中利用IMKVS结合NFV的分布式网络负载均衡策略

社交网络和其他云应用程序应该能对从数据中心发出的请求作出快速响应,实现这种请求的技术之一是内存中的键值存储（IMKVS）,它是一种缓存机制,目的是为了提高整体用户体验。一般地,IMKVS系统使用一致性哈希来决定在哪存储目标,一致性哈希使用起来方法简单,但可能引起网络负载的不平衡。为了提高IMKVS的缓存性能,提出一种软件定义网络中利用IMKVS结合NFV的分布式网络负载均衡策略。该策略包含两个阶段,第一阶段设计通用的SDN负载平衡器的模块,以运行不同的负载平衡算法;第二阶段是基于IMKVS的专业化缓存,可以实现通信管理和数据复制。仿真结果表明,相比于一致性哈希,缓存服务器上的负载可改善24%,网络上的负载可改善7%,策略能够使资源利用更合理,获得更好的用户体验。     

Index-Based Cache Coherence Protocol

A multiprocessor envirorLment may encounter many problems such as deadlock, load balancing and cache coherence. However, the latter is considered the most dangerous if not properly designed, the system works naturally but generates inaccurate results. This occurs if obsolete versions of a memory block are used. Users may not be aware of the presence of such problem. Two main approaches are known to maintain data consistency： namely, snoopy and directory-based protocols. Each approach has its advantages and limitations. This paper proposes a new technique that considers both previously mentioned approaches. The network architecture is slightly updated by adding an index table to each processor. The proposed protocol is expected to reduce the access time, decrease the number of accesses to main memory, maintain data consistency, and assure the usage of the most recent value of a shared variable.