基于多核DSP处理器DM8168的视频处理方法

随着1080P高清视频以及4K超高清晰视频的普及和应用,基于传统单核DSP处理器的视频信息处理已有些力不从心。为此TI公司推出了一款专门用于高清视频处理的多核DSP处理器,它拥有4个不同类型的处理器,使得视频处理达到了一个更高水平。本文分析研究了该处理器的多核DSP结构及应用开发方法,并对多核间的协调工作及负载情况进行了测试分析。     

限定领域口语对话系统中超出领域话语的协处理方法

领域外话语的开放性、口语化以及表达多样性,使得现有的限定领域口语对话系统不能很好地处理超出领域话语。该文提出了一种限定领域口语对话系统协处理方案,基于人工智能标记语言AIML,设计一套理解开放语义用户话语的理解模板,并对未匹配话语基于话语相似度进行理解模板分类,进而采用扩展有限状态自动机处理模式,结合对话流程上下文的状态及信息,实现理解模板到应答模板的转换,改变了单纯模板匹配方法在对话流程控制方面的相对缺失。中文手机导购领域的测试表明,该文所提出的协处理方法能有效地辅助口语对话系统完成限定领域完整对话流程,得到更好的用户满意度。
     

Compact Keccak Hardware Architecture for Data Integrity and Authentication on FPGAs

ABSTRACT

Cryptographic hash functions play a crucial role in networking and communication security, including their use for data integrity and message authentication. Keccak hash algorithm is one of the finalists in the next generation SHA-3 hash algorithm competition. It is based on the sponge construction whose hardware performance is worth investigation. We developed an efficient hardware architecture for the Keccak hash algorithm on Field-Programmable Gate Array (FPGA). Due to the serialization exploited in the proposed architecture, the area needed for its implementation is reduced significantly accompanied by higher efficiency rate. In addition, low latency is attained so that higher operating frequencies can be accessed. We use the coprocessor approach which exploits the use of RAM blocks that exist in most FPGA platforms. For this coprocessor, a new datapath structure allowing parallel execution of multiple instructions is designed. Implementation results prove that our Keccak coprocessor achieves high performance in a small area.     

LDLT分解协处理器的并行结构研究

为提高LDLT分解协处理器的性能,基于FPGA平台,研究其并行结构。分析循环片间的数据依赖关系,提出LDLT分解细粒度并行算法,并在可扩展一维阵列处理器中加以实现,利用主机、算法加速器组成单精度浮点LDLT分解协处理器的并行结构。实验结果表明,与运行在2.50 GHz Pentium微处理器上的C代码相比,该协处理器可获得32.03倍~43.25倍的性能提升。     

A TCAM-based solution for integrated traffic anomaly detection and policy filtering

The survivability of the future Internet is largely dependent on whether it will be able to successfully address both security and performance issues facing the Internet. On one hand, the Internet becomes more and more vulnerable due to fast spreading malicious attacks. On the other hand, it is under great stress to meet ever growing/changing application demands while having to sustain multi-gigabit forwarding performance. In this paper, we propose a Ternary Content Addressable Memory (TCAM) coprocessor based solution for high speed, integrated TCP flow anomaly detection and policy filtering. The attacking packets with spoofed source IP addresses are detected through two-dimensional (2D) matching. The key features of the solution are: (1) setting flag bits in TCAM action code to support various packet treatments; (2) managing TCP flow state in pair to do 2D matching. We evaluate the solution’s ability to detect TCP-based flooding attacks based on real-world-trace simulations. The results show that the proposed solution can match up OC-192 line rate. The possible modifications of the solution for the detection of low rate TCP-targeted attacks are also discussed.     

模糊推理协处理器芯片

模糊推理协处理器VLSI芯片F200采用0.8μm CMOS工艺,作为一种模糊 控制器,主要用于实时过程控制和其它适合的应用场合,例如机器人控制、分类器、专家系 统等.F200芯片支持多个模糊知识库工作,支持最常用的两种模糊模型,Mamdani和 Trakagi-Sugeno模型.芯片精度12位,主频20MHz,推理速度约为每秒1.2M条模糊规则.     

激光光散射谱仪的数据采集与处理系统

介绍了对激光光谱射说仪计算机控制系统进行了更新改造，重新建立包括数据采集，数据处理，图形显示和打印在内的完整的测试分析系统，该系统不仅提高了测量和计算速度 ，而且测量的数据可以被其他软件读取，为利用先进的数据处理软件创造了条件。     

Initial results on computational performance of Intel many integrated core,sandy bridge,and graphical processing unit architectures: implementation of a 1D c++/OpenMP electrostatic particle‐in‐cell code

We present initial comparison performance results for Intel many integrated core (MIC), Sandy Bridge (SB), and graphical processing unit (GPU). A 1D explicit electrostatic particle‐in‐cell code is used to simulate a two‐stream instability in plasma. We compare the computation times for various number of cores/threads and compiler options. The parallelization is implemented via OpenMP with a maximum thread number of 128. Parallelization and vectorization on the GPU is achieved with modifying the code syntax for compatibility with CUDA. We assess the speedup due to various auto‐vectorization and optimization level compiler options. Our results show that the MIC is several times slower than SB for a single thread, and it becomes faster than SB when the number of cores increases with vectorization switched on. The compute times for the GPU are consistently about six to seven times faster than the ones for MIC. Compared with SB, the GPU is about two times faster for a single thread and about an order of magnitude faster for 128 threads. The net speedup, however, for MIC and GPU are almost the same. An initial attempt to offload parts of the code to the MIC coprocessor shows that there is an optimal number of threads where the speedup reaches a maximum. Copyright © 2014 John Wiley & Sons, Ltd.     

一种模拟协处理器的实现架构

提出了一种模拟协处理器的设计思想,介绍了一种利用成熟模拟电路的运算特性进行波形变换,并实现高速复杂波形的方法。即先利用DSP的灵活性产生一种低阶的简单波形,再利用成熟模拟电路的运算特性(如对数运算、乘方运算、微/积分运算等)将前级电路产生的简单波形变换为所需的高阶复杂波形。由于模拟协处理器的应用,DSP的计算任务由计算超越函数简化为计算非超越函数,计算量和采样点数都大幅减少,使得常规的DSP芯片就能够完成必要的波形计算和其它任务(如编码运算)。该方法结合了数字电路和模拟电路各自的优势,能够消除数字电路(如DSP、DDS等)实现一些高速复杂调制时常见的几种数字波纹。工程实践和MATLAB仿真证明,此设计思想具有良好的推广和应用价值。     

图像Laplace变换在异构多核工程科学计算加速协处理器上的实现

基于自主研发的新颖异构多核工程科学计算加速协处理器（ESCA）体系结构,实现了图像Laplace变换算法。针对ESCA架构特点,采用子字并行计算和访存延迟隐藏等机制,进行了一系列并行算法优化,并在四核ESCA处理器原型上对图像Laplace变换算法的进行了性能评测。实验结果表明,对于计算密集型计算任务,ESCA处理器具有良好的计算加速效果。