A review of the existing performance verification infrastructure for micro-CMMs

The performance verification of micro-CMMs is now of intense interest because of their capability to perform length measurements in three dimensions to high accuracy with low uncertainties. Currently, verification of micro-CMMs is completed in the spirit of existing specification standards, because strict adherence to these standards is often difficult. This review aims to present and discuss verification techniques available for micro-CMMs: specification standards, existing calibrated test lengths and traceability routes that can be associated with micro-CMMs. Three specification standards used in the testing of CMMs will be considered. In addition, a wide range of calibrated test lengths are reported, and any advantages and disadvantages associated with their use are discussed. It is concluded that micro-CMMs cannot yet be verified in accordance with existing specification standards. Suggestions are made for future standardisation work required to rectify these issues.     

嵌入式实时操作系统内核混合代码的自动化验证框架

"如何构造高可信的软件系统"已成为学术界和工业界的研究热点.操作系统内核作为软件系统的基础组件，它的安全可靠是构造高可信软件系统的重要环节.为了确保操作系统内核的安全可靠，将形式化方法引入到操作系统内核验证中，提出了一个自动化验证操作系统内核的框架.该验证框架包括：（1）分别对C语言程序和混合语言程序（C语言和汇编语言）进行验证；（2）在混合语言程序验证中，为汇编程序建立抽象模型，并将C语言程序和抽象模型粘合形成基于C语言验证工具可接收的验证模型；（3）从规范中提取性质，基于该自动验证工具，对性质完成自动验证；（4）该框架不限于特定的硬件架构.成功地运用该验证框架对两种不同硬件平台的嵌入式实时操作系统内核μC/OS-II进行了验证.结果显示：利用该框架在对两个不同的硬件平台上内核验证时，框架的可重复利用率很高，高达到88%，虽然其抽象模型需要根据不同的硬件平台进行重构.在对基于这两种平台的操作系统内核验证中，分别发现了10~12处缺陷.其中，在ARM平台上两处与硬件相关的问题被发现.实验表明，该方法对不同硬件平台的同一个操作系统分析验证具有一定的通用性.     

Multi-resource scheduling for FPGA systems

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.     

Methods of Verifying Continuous Automatic Belt Weighers: State and Prospects

The basic methods of verifying continuous automatic belt weighers are described. A comparative analysis of these methods on the basis of experimental studies is made and ways of implementing the results in industry are recommended.     

动力环境集中监控系统可靠性的提高

为实现电源设备乃至通信机房的少人或无人值守和集中维护,必须建立一套完善的电信局动力环境集中监控系统。文中结合番禺区电信局的实际,讨论了提高系统运行可靠性的几点措施,包括硬件方面与软件方面的手段,关键在于加强系统的运行管理。     

Development of a safety critical software requirements verification method with combined CPN and PVS: a nuclear power plant protection system application

Safety-critical software systems such as certain nuclear instrumentation and control (NI&C) systems should be developed with thorough verification. This study presents a method of software requirement verification with a case study for a nuclear power plant (NPP) protection system. The verification introduces colored petri net (CPN) for system modeling and prototype verification system (PVS) for mathematical verification. In order to aid flow-through from modeling by CPN to mathematical proof by PVS, an information extractor from CPN models has been developed in this paper. In order to convert the extracted information to the PVS specification language, a translator has also been developed. This combined method has been applied to the functional requirements of the Wolsong NPP Shut Down System #2 (SDS2); logical properties of the requirements were verified. Through this research, guidelines and a tool support for the use of formal methods have been developed for application to NI&C software verification.     

分组密码算法芯片验证

介绍了分组密码算法芯片验证的流程、内容和方法,详细介绍了分组密码算法芯片的验证技术——测试基准。     

对基于交换网络分层结构的软件无线电方案的改进

通过比较各种软件无线电结构的优缺点,针对既具有交换网络结构又具有分层结构优点的基于交换网络的分层无线电结构方案,提出了部分改进思想。     

Reconfigurable hardware implementation of a phase-correlation stereoalgorithm

This paper describes the implementation of a stereo-vision system using Field Programmable Gate Arrays (FPGAs). Reconfigurable hardware, including FPGAs, is an attractive platform for implementing vision algorithms due to its ability to exploit parallelism often found in these algorithms, and due to the speed with which applications can be developed as compared to hardware. The system outputs 8-bit, subpixel disparity estimates for 256× 360 pixel images at 30,fps. A local-weighted phase correlation algorithm for stereo disparity [Fleet, D. J.: {Int. Conf. Syst. Man Cybernetics 1:48–54 (1994)] is implemented. Despite the complexity of performing correlations on multiscale, multiorientation phase data, the system runs as much as 300 times faster in hardware than its software implementation. This paper describes the hardware platform used, the algorithm, and the issues encountered during its hardware implementation. Of particular interest is the implementation of multiscale, steerable filters, which are widely used in computer vision algorithms. Several trade-offs (reducing the number of filter orientations from three to two, using fixed-point computation, changing the location of one localized low-pass filter, and using L1 instead of L2 norms) were required to both fit the design into the available hardware and to achieve video-rate processing. Finally, results from the system are given both for synthetic data sets as well as several standard stereo-pair test images.     

基于重量分析的OBDD变量排序算法

有序的二叉判决图（ＯＢＤＤ）是布尔表达式的一种有效表示方法，但它的体积对变量排序具有较强的依赖性。本文提出一种电路结构图，并在此基础上定义了原始输入重量和节点重量等参数，并建立了用重量分析来指导的ＯＢＤＤ变量排序算法。由于从考虑变量对输出函数的影响出发与从考虑ＯＢＤＤ节点共享性出发对变量排序的要求不同，本文分别设计了两类算法。实验结果表明，本文对大多数标准电路变量排序的效果都优于国际上的同类算法，