Cell处理器访存特征研究

Cell处理器是一款异构多核处理器,拥有强大的计算能力。但是,在进行应用并行化时,却受到本地存储器容量、访存带宽和数据传输延时等的限制。DMA传输是隐藏长延时、提高存储带宽利用率的有效方法。本文在分析Cell处理器结构基础上,进行了一系列详细的DMA测试,并利用指数拟合技术得到DMA平均带宽模型,发现参与DMA传输的SPE数量和每次DMA传输规模是影响DMA访存带宽的主要因素。     

Accelerating sequential programs on commodity multi-core processors

A recently proposed pipelined multithreading (PMT) technique exhibits wide applicability in parallelizing general sequential programs on multi-core processors. However, significant inter-core communication overhead limits PMT performance and prevents its commercial utilization. A simple and effective clustered pipelined multithreading (CPMT) approach is presented to accelerate sequential programs on commodity multi-core processors. This CPMT technique adopts a clustered communication mechanism that can yield very low average communication overhead by eliminating false sharing as well as reducing communication operation and transit delays in the software-only approach. A single-producer/single-consumer concurrent lock-free clusteredQueue algorithm based on a two-level queue structure is also proposed. The accuracy of CPMT is theoretically demonstrated. The performances of the algorithm and CPMT are evaluated on a commodity AMD Phenom four-core processor. The number of enqueue and dequeue times of the algorithm are 20.8 and 23 cycles given an appropriate parameter, respectively. The speedup of CPMT ranges from 13.1% to 119.8% for typical loops extracted from the SPEC CPU 2000 benchmark suite.     

OpenMDSP: Extending OpenMP to Program Multi-Core DSPs

Abstract Multi-core digital signal processors （DSPs） are widely used in wireless telecommunication, core network transcoding, industrial control, and audio/video processing technologies, among others. In comparison with general-purpose multi-processors, multi-core DSPs normally have a more complex memory hierarchy, such as on-chip core-local memory and non-cache-coherent shared memory. As a result, efficient multi-core DSP applications are very difficult to write. The current approach used to program multi-core DSPs is based on proprietary vendor software development kits （SDKs）, which only provide low-level, non-portable primitives. While it is acceptable to write coarse-grained task-level parallel code with these SDKs, writing fine-grained data parallel code with SDKs is a very tedious and error-prone approach. We believe that it is desirable to possess a high-level and portable parallel programming model for multi-core DSPs. In this paper, we propose OpenMDSP, an extension of OpenMP designed for multi-core DSPs. The goal of OpenMDSP is to fill the gap between the OpenMP memory model and the memory hierarchy of multi-core DSPs. We propose three classes of directives in OpenMDSP, including 1） data placement directives that allow programmers to control the placement of global variables conveniently, 2） distributed array directives that divide a whole array into sections and promote the sections into core-local memory to improve performance, and 3） stream access directives that promote big arrays into core-local memory section by section during parallel loop processing while hiding the latency of data movement by the direct memory access （DMA） of a DSP. We implement the compiler and runtime system for OpenMDSP on PreeScale MSC8156. The benchmarking results show that seven of nine benchmarks achieve a speedup of more than a factor of 5 when using six threads.     

基于同构多核处理器的任务调度

随着现代应用对计算机性能要求的提高,计算机主频不断提升。由于功耗和半导体工艺的限制,仅靠提高单核主频难以继续维持“摩尔定律”,同构多核处理器（Homogeneous Multi-core）应运而生。在同构多核处理器的支持下,一个芯片汇集多个地位对等、结构相同的通用处理器核,以最小的代价满足了提高系统性能、负载均衡、处理器容错的需要。并行体系结构需要结合与之适应的软件实现性能效益的倍增。本文从操作系统层面,针对处理器结构的变化,研究并实现多核任务调度。系统采用混合调度策略,簇间独立调度,簇内统一调度。从调度模式、调度算法、分配算法、调度时机等方面详细分析了多核调度的原理和实现机制。最后通过模拟实验证明功能正确性及算法可调度性。     

一种针对依赖性周期任务的实时多核调度算法

针对软实时系统中的一类同时具有依赖性与周期性的任务,提出一种基于单行树矩阵(MST)的动态因子均衡调度算法SMD(schedule on matrix of the single tree and dynamic load factor)。该算法通过对MST矩阵的特性进行分析,将任务划分为若干并行集,再综合考虑已执行时间、任务间的依赖关系及任务最早截止时间几个要素,以动态因子的形式对任务进行实时调度。最后,还以证明的形式给出了可充分调动的任务集的充分条件,并以此为基础随机生成了测试任务集,进行了对比实验。实验表明,与文献中现有经典算法相比,新算法使处理器利用率提升近15%,任务丢失率降低2%。     

基于多核DSP处理器DM8168的视频处理方法

随着1080P高清视频以及4K超高清晰视频的普及和应用,基于传统单核DSP处理器的视频信息处理已有些力不从心。为此TI公司推出了一款专门用于高清视频处理的多核DSP处理器,它拥有4个不同类型的处理器,使得视频处理达到了一个更高水平。本文分析研究了该处理器的多核DSP结构及应用开发方法,并对多核间的协调工作及负载情况进行了测试分析。     

多核DSP的以太网远程程序加载方法

为了解决工业远程控制设备的软件更新带来的成本和效率问题,在研究了以TMS320C6670为核心的DSP系统的结构和程序启动的基础上,提出了基于以太网的DSP程序远程加载方法。该方法主要基于BOOTP协议的广播和以太网UDP协议实现。实践表明,该加载技术灵活可靠,为远程控制系统的调试和更新提供了便利。     

异构多核处理器的任务分配及能耗的研究*

异构多核处理器采用不同的任务分配与调度算法,会导致不同的时间消耗与能量消耗,采用合适的任务分配与调度算法能节省较多的能耗。目前普遍认为最有发展前途的任务分配与调度技术是先用启发式方法进行分组,然后再用遗传算法进行调度。在改进任务分组后,又首次提出了用遗传算法解决能耗问题。实验结果表明在实时要求不高的情况下,能以较小的时间代价来节省较多的能耗。     

Limited carry-in technique for real-time multi-core scheduling

Schedulability analysis has been widely studied to provide offline timing guarantees for a set of real-time tasks. The so-called limited carry-in technique, which can be orthogonally incorporated into many different multi-core schedulability analysis methods, was originally introduced for Earliest Deadline First (EDF) scheduling to derive a tighter bound on the amount of interference of carry-in jobs at the expense of investigating a pseudo-polynomial number of intervals. This technique has been later adapted for Fixed-Priority (FP) scheduling to obtain the carry-in bound efficiently by examining only one interval, leading to a significant improvement in multi-core schedulability analysis. However, such a successful result has not yet been transferred to any other non-FP scheduling algorithms. Motivated by this, this paper presents a generic limited carry-in technique that is applicable to any work-conserving algorithms. Specifically, this paper derives a carry-in bound in an algorithm-independent manner and demonstrates how to apply the bound to existing non-FP schedulability analysis methods for better schedulability.     

基于OCTEON芯片的高精度流回放系统的设计与实现

介绍网络多核处理器OCTEON和基于OCTEON开发的基本需求,讨论在Linux平台下基于该芯片开发高精度流回放系统的设计与实现过程,包括主机与OCTEON间PCI的通信,高精度流回放的时间戳实现,以及多个流同时回放的设计与实现。对该系统的性能测试表明,基于OCTEON的流回放实现高度并行并且高精度的处理,系统的实现对于在高速Gbps环境下的网络数据流检测、过滤与入侵检测系统具有很高的应用价值。