RF/wireless-interconnect: The next wave of connectivity

In the era of the nanometer CMOS technology, due to stringent system requirements in power, performance and other fundamental physical limitations (such as mechanical reliability, thermal constraints, overall system form factor, etc.), future VLSI systems are relying more on ultra-high data rates (up to 100 Gbps/pin or 20 Tbps aggregate), scalable, re-configurable, highly compact and reliable interconnect fabric. To overcome such challenges, we first explore the use of multiband RF/wireless-interconnects wh...     

复用NoC测试SoC内嵌IP芯核的测试规划研究

测试规划是SoC芯片测试中需要解决的一个重要问题。一种复用片上网络测试内嵌IP芯核的测试规划方法被用于限制测试模式下SoC芯片功耗不超出最大芯片功耗范围,消除测试资源共享所引起的冲突,达到减小测试时间的目的。提出了支持测试规划的无拥塞路由算法和测试扫描链优化配置方法。使用VHDL硬件描述语言实现了在FPGA芯片中可综合的二维Mesh片上网络测试平台,用于片上网络性能参数、路由算法以及基于片上网络的SoC芯片测试方法的分析评估。     

Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips

A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.     

片上网络路由器的交叉开关设计实现

交叉开关是片上网络路由器的关键部分。交叉开关的设计可以采用三态触发器或多路复用器实现。本文针对几种不同形式的交叉开关实现方案,比较了其面积和功耗的开销,同时设计了基于iSLIP算法的交叉开关调度机制。通过基本逻辑门搭建的多路复用器实现的交叉开关相比于采用三态门实现的交叉开关,在功耗、面积上有较大优势。采用iSLIP算法实现的片上网络交叉开关,具有最高的工作频率上限。     

用于片上网络的全异步串行连接转换器

针对传统片上网络路由器之间互连线过多,传输功耗大的缺陷,提出了一种用于全异步片上网络的串行传输转换器。通过将路由器之间的并行数据分组并以更小的数据块传输,使得片上路由之间的互连线成倍减少,并可以大大减小传输过程带来的功率损耗。零协议逻辑门限门的应用使电路准延时不敏感,提高了转换器的鲁棒性。基于SMIC 0.18μm标准CMOS工艺实现了此串行连接转换器及串行通道。结果表明,在32位数据位宽下,此全异步串行连接转换器可节约路由器之间近3/4的连线资源以及减少近2/3的功耗。此全异步串行连接转换器适用于对面积和功耗较为敏感的片上网络互连应用。     

A full asynchronous serial transmission converter for network-on-chips

Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power overheads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.