Design of Feedback Shift Register of Against Power Analysis Attack

Stream ciphers based on linear feedback shift register (LFSR) are suitable for constrained environments, such as satellite communications, radio frequency identification devices tag, sensor networks and Internet of Things, due to its simple hardware structures, high speed encryption and lower power consumption. LFSR, as a cryptographic primitive, has been used to generate a maximum period sequence. Because the switching of the status bits is regular, the power consumption of the LFSR is correlated in a linear way. As a result, the power consumption characteristics of stream cipher based on LFSR are vulnerable to leaking initialization vectors under the power attacks. In this paper, a new design of LFSR against power attacks is proposed. The power consumption characteristics of LFSR can be masked by using an additional LFSR and confused by adding a new filter Boolean function and a flip-flop. The design method has been implemented easily by circuits in this new design in comparison with the others.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

CRC计算方法的研究

本文丛面地介绍了ＣＲＣ的基本原理和计算方法，并给出了编程实例。     

基于移位原理的顺序控制器研究

本文根据PLC顺序控制程序的设计思路,阐述了用常用集成数码移位寄存器、电力电子开关电路和少量外围电子元件构成移位控制器的原理,根据此设计思路制作的移位控制器经过在实验室环境下运行,证明了设计方案的可行性。     

移动IP的关键技术

本详细描述了移动IP的工作过程，并介绍了移动IP的隧道技术和IPSec，最后对移动IP技术中存在几个热点问题进行了讨论。     

医院排队叫号系统应用现状综述

为了减少患者在医院的滞留量和高效服务于患者,很多医院都采用了排队叫号系统。医院排队叫号系统产品繁多,医院的实施机制也各不相同,因此分析了目前医院排队叫号系统的应用现状,以及硬、软件实施情况,以求发现系统的主要组成部分和可更新、扩展部分。结合挂号方式、就诊流程优化和物联网技术分析了医院排队叫号系统的发展趋势,这对今后其他领域排队叫号系统的研究有参考意义。     

Concurrent reading while writing revisited

A modification is proposed to Peterson's construction of 1-writern-reader multivalued atomic shared variableusingn+2 multivalued safe variables and some boolean atomic variables. The resulting construction is elegant and is simpler than the original one. K. Vidyasankar received B.E. (Elec. Engg.) from Thiagarajar College of Engineering, Madurai, M. Tech. from I.I.T. Kanpur, India, and Ph.D. in Computer Science from University of Waterloo, Canada. He is now an Associate Professor in Computer Science at Memorial University of Newfoundland, Canada. His research interests include concurrency control and recovery in database systems, concurrency in interprocess communication, design and analysis of algorithms, and graph theory.A prelininary version of this paper, under the title Improving Peterson's Construction of 1-Writern-Reader Multivalued Atomic Register, appears in the Proc. 26th Annual Allerton Conference on Communication, Control, and Computing, University of Illinois at Urbana Champaign, September 1988, pp 693–700     

基于SoC的嵌入式DRAM存储器内建自测试设计

内建自测试(Built-in Self Test,BIST)是测试片上系统(System on- Chip,SoC)中嵌入式存储器的重要技术;但是,利用BIST技术采用多种算法对嵌入式存储器进行测试仍面临诸多挑战;对此,提出了一种基于SoC的可以带有多种测试算法的嵌入式DRAM存储器BIST设计,所设计的测试电路可以复用状态机的状态,利用循环移位寄存器(Cyclic Shift Register,CSR)产生操作命令,利用地址产生电路产生所需地址;通过对3种BIST电路支持的算法,全速测试,面积开销3个方面的比较,表明提出的嵌入式DRAM存储器BIST设计在测试时间,测试故障覆盖率和测试面积开销等各方面都取得了较好的性能.     

SPI总线扩展PLC输出点数的设计与实现

针对PLC主模块可用输出点数少的缺点,提出了采用SPI总线和移位寄存器HC595相结合扩展PLC输出点数,并设计了输出扩展电路;根据SPI总线及HC595的时序特点,确定了SPI的时钟模式,解决了时序的配合问题,并确定了输出点数的逻辑顺序;UDTY端接一下拉电阻,保证其处于高电平,SPI2CLK信号取反后输入到HC595,保证其采样到稳定的SPI输出数据,滤波电容,提高了电路抗干扰性能;编程实现对扩展输出点数的控制。实际应用表明,该设计方案经济、可靠。