超标量处理器乱序提交机制的研究与设计

针对超标量处理器中长周期执行指令延迟退休及持续译码导致的重排序缓存（ROB）阻塞问题,提出一种指令乱序提交机制。通过设计容量可配置的多缓存指令提交结构,实现存储器操作指令和ALU类型指令的分类退休,根据超标量处理器架构及性能需求对目标缓存和存储缓存容量进行参数化配置降低流水线阻塞风险,同时利用指令目的寄存器编码提交模式加快指令提交速率。实验结果表明,该机制提高了单次指令提交数量,基于该机制的超标量处理器相比传统基于ROB顺序提交机制的超标量处理器在减少硬件开销的情况下平均IPC指数提升46%,相比基于值预测、乱序退休和组提交的超标量处理器平均IPC指数增益为19%,综合性能更优。     

流水线前端资源分配及其性能影响研究

动态超标量处理器的性能取决于流水线各段资源的配置情况,通常认为资源越多对性能提升越有利。对流水线前端资源的分配进行研究,发现各类资源的合理搭配更重要,资源配置过多或搭配不当可能产生负面影响。分析各类资源的潜在互相干扰、影响性能的现象、过程及深层次原因,并给出一些参考建议。     

Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits

A concept for a future integer arithmetic unit suitable for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits is presented. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. This allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A transistor layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technology. Furthermore we present results we gained by investigations on a first realized optoelectronic VLSI test chip.     

WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets

Determining a tight WCET of a block of code to be executed on a modern superscalar processor architecture is becoming ever more difficult due to the dynamic behaviour exhibited by current processors, which include dynamic scheduling features such as speculative and out-of-order execution in the context of multiple execution units with deep pipelines. We describe the use of Coloured Petri Nets (CP-nets) in a simulation based approach to this problem. A complex model of a generic processor architecture is described, with emphasis on the modelling strategy for obtaining the WCET and an analysis of the results.     

一种硬件预取机构及其对系统影响的研究

存储器访问延迟已经成为高性能微处理器性能发挥的关键障碍之一。预取是隐藏访存延迟的重要手段。其通常做法是显式执行指令将数据在实际使用前先和取到离微处理器附近的地方,但是这种方法增加了程序设计人员的负担。本文提出了一种硬件预取方法,即在存储控制器中设计一个VPFB机构用来隐藏访存延迟,并通过模拟分析了它的效果。     

一种静态LoC关键性预测器设计

针对不同分簇超标量处理器结构下SPEC2000程序中指令关键可能性(LoC)的特性,提出一种静态LoC关键性预测器的设计方法。对指令LoC进行研究,根据其结构无关性和动态不变性,设计预测器。仿真结果表明,在对1×8分簇超标量处理器使用该设计时,程序的每周期指令数平均提升5.3%,性能优于动态LoC预测器。     

基于RISC-V参数化超标量处理器的优化设计

为解决嵌入式领域对处理器不同性能面积的需求,以及对重排序缓冲区阻塞,保留站派遣长短周期指令时导致的吞吐率不平衡及堵塞问题,设计并优化了一种简便配置的参数化流水线超标量处理器.通过定制化流水线中的分支预测,缓存与运算单元,将RISC-V指令划分5大类处理,对不同周期的执行单元采用级联与并行的混合分布方式,将充当排序缓存中...     

铝合金热轧带材“中凸度超标＋中间波浪”板形缺陷的原因分析与改进措施

试验研究了单机架双卷取四辊可逆热轧机生产5182铝合金时,产生＂中凸度超标＋中间波浪＂缺陷的原因。结果表明：工作辊原始凸度太小、道次压下量不合理、乳液喷淋压力太小是导致产生该缺陷的主要原因。通过增大工作辊原始凸度、优化道次压下量、提高乳液喷淋压力可以消除此缺陷。     

Performance evaluation of the SX‐6 vector architecture for scientific computations

The growing gap between sustained and peak performance for scientific applications is a well‐known problem in high‐performance computing. The recent development of parallel vector systems offers the potential to reduce this gap for many computational science codes and deliver a substantial increase in computing capabilities. This paper examines the intranode performance of the NEC SX‐6 vector processor, and compares it against the cache‐based IBM Power3 and Power4 superscalar architectures, across a number of key scientific computing areas. First, we present the performance of a microbenchmark suite that examines many low‐level machine characteristics. Next, we study the behavior of the NAS Parallel Benchmarks. Finally, we evaluate the performance of several scientific computing codes. Overall results demonstrate that the SX‐6 achieves high performance on a large fraction of our application suite and often significantly outperforms the cache‐based architectures. However, certain classes of applications are not easily amenable to vectorization and would require extensive algorithm and implementation reengineering to utilize the SX‐6 effectively. Copyright © 2005 John Wiley & Sons, Ltd.     

Performance of computationally intensive parameter sweep applications on Internet‐based Grids of computers: the mapping of molecular potential energy hypersurfaces

This work focuses on the use of computational Grids for processing the large set of jobs arising in parameter sweep applications. In particular, we tackle the mapping of molecular potential energy hypersurfaces. For computationally intensive parameter sweep problems, performance models are developed to compare the parallel computation in a multiprocessor system with the computation on an Internet‐based Grid of computers. We find that the relative performance of the Grid approach increases with the number of processors, being independent of the number of jobs. The experimental data, obtained using electronic structure calculations, fit the proposed performance expressions accurately. To automate the mapping of potential energy hypersurfaces, an application based on GRID superscalar is developed. It is tested on the prototypical case of the internal dynamics of acetone. Copyright © 2006 John Wiley & Sons, Ltd.