Simulations of Sub-100 nm Strained Si MOSFETs with High-κ Gate Stacks

By including soft-optical phonon scattering within an ensemble Monte Carlo simulator, this paper studies the impact of high-κ gate stacks on the performance of n-type Si and strained Si MOSFETs. The simulated devices replicate the performance of sub-100 nm Si and strained Si MOSFETs fabricated by IBM. The results indicate a significant reduction in the device performance due to the presence of a high-κ gate dielectric in both Si and strained Si transistors.