首页 | 本学科首页   官方微博 | 高级检索  
     

FAME:一个标准单元模式下基于最小割和枚举的快速详细布局算法
引用本文:姚波,侯文婷.FAME:一个标准单元模式下基于最小割和枚举的快速详细布局算法[J].半导体学报,2000,21(8):744-753.
作者姓名:姚波  侯文婷
作者单位:姚波(清华大学计算机科学与技术系,北京 100084)       侯文婷(清华大学计算机科学与技术系,北京 100084)       洪先龙(清华大学计算机科学与技术系,北京 100084)       蔡懿慈(清华大学计算机科学与技术系,北京 100084)
基金项目:* Project Supported by National Natural Science Foundation of China (Grant No. 69776027) and by National 973 Key Project of China (Contract No. G1998030413)
摘    要:随着制造工艺的快速进步,超大规模集成电路的物理设计技术在速度和质量上面临很大挑战。提出了一个快速详细布局算法以适应这种要求,算法继续总体布局得到的单元全局最佳位置,然后采用局部优化将单元精确定位。FM最小割和局部枚举方法分别用于优化y和x两个方面的连线长度,这两个方向的同一迭代过程中交替进行。另外,采用改进的枚举策略加速算法,对于有障碍和宏模块情况下的布局也加以讨论,实例测试结果表明,FAME的运

关 键 词:详细布局  超大规模集成电路  最小割  枚举  FAME
文章编号:0253-4177(2000)08-0744-10
修稿时间:1999-12-30

Fame:A Fast Detailed Placement Algorithm for Standard Cell Layout Based on Mixed Mincut and Enumeration
YAO B ,HOU Wen-ting ,HONG Xian-long ,CAI Yi-ci.Fame:A Fast Detailed Placement Algorithm for Standard Cell Layout Based on Mixed Mincut and Enumeration[J].Chinese Journal of Semiconductors,2000,21(8):744-753.
Authors:YAO B  HOU Wen-ting  HONG Xian-long  CAI Yi-ci
Affiliation:YAO B0 ,HOU Wen-ting ,HONG Xian-long ,CAI Yi-ci (Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China)
Abstract:Rapid progress in manufacturing greatly challenges to the VLSI physical design in both speed and performance. A fast detailed placement algorithm, FAME is presented in this paper, according to these demands. It inherits the optimal positions of cells given by a global placer and exact position to each cell by local optimization. FM Mincut heuristic and local enumeration are used to optimize the total wirelength in y and x directions respectively, and a twoway mixed optimizing flow is adopted to combine the two methods for a better performance.Furthermore, a better enumeration strategy is introduced to speed up the algorithm. An extension dealing with blockages in placement has also been discussed. Experimental results show that FAME runs 4 times faster than RITUAL and achieves a 5% short in total wirelength on average.
Keywords:detailed placement  layout  VLSI  mincut  optimization
本文献已被 维普 等数据库收录!
点击此处可从《半导体学报》浏览原始摘要信息
点击此处可从《半导体学报》下载全文
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号