Compact wide bandwidth dual-port DRAM architecture suitable for mobile multimedia processors |
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Authors: | Hong S |
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Affiliation: | KyungHee Univ., Yongin; |
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Abstract: | A DRAM architecture capable of providing dual-port interface is presented. The architecture utilises a novel global bitline scheme to obtain a very wide data bandwidth not possible using traditional DRAM architectures. Furthermore, the area penalty is minimised by using a conventional one-transistor one-capacitor cell coupled with special sensing units that have 84.6% more transistor count. The architecture allows simultaneous read and write access using a conventional two-metal DRAM fabrication process. |
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