A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-μm CMOS. An opampsharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB (ENOB =9.69 bits) and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.