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Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET
Authors:Ashwani KRana  Narottam Chand  Vinod Kapoor
Affiliation:1. Department of Electronics and Communication, National Institute of Technology, Hamirpur, Hamirpur(H.P)-177005, India
2. Department of Computer Science and Engineering, National Institute of Technology, Hamirpur, Hamirpur(H.P.)-177005, India
Abstract:A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D(source/drain) region.It is found that an optimal so...
Keywords:gate tunneling current  analytical model  spacer dielectrics  DIBL  subthreshold slope  
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