| 基于硬件协议栈芯片的高速以太网接口设计 |
| |
| 引用本文： | 宋飞,冯旭哲. 基于硬件协议栈芯片的高速以太网接口设计[J]. 工业仪表与自动化装置, 2012, 0(4): 57-59 |
| |
| 作者姓名： | 宋飞 冯旭哲 |
| |
| 作者单位： | 国防科技大学 仪器科学与技术系,长沙,410073 |
| |
| 摘 要： | 随着现代数据采集系统和测试系统对信息传输速率的更高要求,网络化数据传输成为未来发展的趋势。采用Xilinx公司的XC5VLX50型FPGA和硬件协议栈芯片W5300开发了一种以太网接口,结构简单、易于实现。给出了以太网接口的硬件设计,阐明了硬件协议栈芯片初始化、端口初始化以及数据传输的软件实现;并对读写寄存器时序进行了详细阐述。实验表明该设计能够稳定的进行数据传输,实现了FPGA和上位机之间的通信。
|
| 关 键 词： | FPGA W5300 以太网 UDP |
Design of the fast Ethernet interface based on hardware protocol stack chip |
| |
| SONG Fei , FENG Xuzhe. Design of the fast Ethernet interface based on hardware protocol stack chip[J]. Industrial Instrumentation & Automation, 2012, 0(4): 57-59 |
| |
| Authors: | SONG Fei FENG Xuzhe |
| |
| Affiliation: | (Department of Instrumental Science and Technology, National University of Defense Technology, Changsha 410073, China) |
| |
| Abstract: | Along with higher demands for the information transmission rate of modern data acquisition system and test system, the Ethernet hardware interface is development trend. The Ethernet interface based on XCSVLX50 FPGA of Xilinx company and hardware protocol stack W5300 chip, and the structure is simple, easy to implement. This paper introduce the design of hardware, illustrate the software implementation of hardware protocol stack chip initialization, socket initialization, data transmission. The timing of reading and writing register is elaborated. The experiment results show that the design can achieve stable data transmission, and implement the communication. |
| |
| Keywords: | FPGA W5300 Ethernet UDP |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
