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三相SPWM变频控制器通用IP核的研究
引用本文:周媛,李铁才,杨贵杰. 三相SPWM变频控制器通用IP核的研究[J]. 哈尔滨理工大学学报, 2004, 9(5): 25-28
作者姓名:周媛  李铁才  杨贵杰
作者单位:天津工程师范学院,自动化工程系,天津,300222;哈尔滨工业大学,电气工程系,黑龙江,哈尔滨,150001
摘    要:针对复杂的电机驱动控制系统对集成化和速度等级的要求,基于EDA技术,利用Altera公司的Qlmrtus Ⅱ软件及EP1K50QC208-3芯片,并采用分时复用的思想和VerilogHDL硬件描述语言设计了基于FPGA的三相SPWM变频控制器的IP核,给出了存储单元和占空比计算单元的设计方法,并进行了仿真与实验分析.存储单元和占空比计算单元的设计中,实验结果表明,该设计完全可以满足电机驱动和变频电源的实时控制要求,且开关频率、死区时间等参数可在线修改,具有开发周期短,可靠性高等特点.

关 键 词:变频控制器  FPGA  IP核  分时复用
文章编号:1007-2683(2004)05-0025-04
修稿时间:2004-05-17

Research on FPGA-based 3-Phase Sinusoidal PWM VVVF Controller General-purpose IP Core
ZHOU Yuan,LI Tie-cai,YANG Gui-jie. Research on FPGA-based 3-Phase Sinusoidal PWM VVVF Controller General-purpose IP Core[J]. Journal of Harbin University of Science and Technology, 2004, 9(5): 25-28
Authors:ZHOU Yuan  LI Tie-cai  YANG Gui-jie
Abstract:Aiming at the demand in integration and speed level of complicated motor driving control system, in this research, an FPGA -based 3 -phase sinusoidal PWM WVF controller IP core is designed by using EDA technique. The design takes full advantage of QuartusII software of Altera Company. And the hardware circuit is realized in the EP1K50QC208-3 chip. VerilogHDL is used to describe the logical circuit designed in the research. Meanwhile, simulation and experimental analysis has been done. To save the chip resource, a thought of time -sharing is applied in the design of memory unit and duty ration calculating unit. The result of the experiment shows that this design can fully meet the demand of electrical machine driving and variable - frequency power sources.
Keywords:VVVF controller  FPGA  IP core  time-sharing
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