An improved maximally redundant signed digit adder

Signed digit (SD) number systems support digit-parallel carry-free addition, where the sum digits absorb the possible signed carries in {−1, 0, 1}. Radix-2^h maximally redundant SD (MRSD) number systems are particularly attractive. The reason is that, with the minimal (h + 1) bits per SD, maximum range is achieved. There are speculative MRSD adders that trade increased area and power for higher speed, via simultaneous computation of three sum digits, while anticipating one of the possible signed carries. However, the nonspeculative approach that uses carry-save two’s complement encoding for intermediate sum digits, has proved to be more efficient.In this paper, we examine three previous nonspeculative MRSD adders and offer an improved design with significant savings in latency, area consumption and power dissipation. The enhanced performance is mainly due to the elimination of sign extension of the signed carries. The latter leads to a sum matrix of positively and negatively weighted bits that normally complicate the use of standard adder cells. However, with inverted encoding of negatively weighted bits, we manage to efficiently use such cells. The claimed performance measures are supported by 0.13 μm CMOS technology synthesis.