Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs |
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| Authors: | Kishine K. Onodera H. |
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| Affiliation: | NTT Microsyst. Integration Labs., Atsugi, Japan; |
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| Abstract: | A method to estimate the acquisition time for the clock and data recovery (CDR) IC using the linear phase-locked loop (PLL) technique is proposed. Estimations using the method follow the measured acquisition time for the PLL with any loop parameters, which makes it possible to design the CDR IC for various targets. |
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