FPGA的1553B总线编码IP核设计

利用FPGA丰富的逻辑资源,设计符合1553B总线编码特征的IP核.首先,研究1553B总线数据格式及编码特征.然后,采用美国XILINX公司的ZYNQ-7000系列FPGA和与之配套的VIVADO开发平台,对1553B总线编码的逻辑电路进行设计.最后,利用VIVADO开发平台的时序仿真功能,对1553B总线编码的逻辑电路进行仿真验证.经过对仿真波形的分析,证明了基于ZYNQ-7000系列FPGA的1553B总线编码IP核能够按照1553B总线数据格式发送1553B总线数据.

I P-core Design of 1553B Bus Encoding Based on FPGA

The IP core in accordance with the features of 1553B is designed using FPGA in the paper.Firstly,the 1553B bus data format and encoding features are researched.Secondly,the logic circuit of 1553B bus encoding is designed using the ZYNQ-7000 serise FPGA and VIVADO development kits.Finally,the 1553B bus encoding logic circuit is simulated and verified using the VIVADO's timing simu-lation.The simulation waveforms prove that the 1553B bus encoding IP core can send the data in accordance with the 1553B bus data format.