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Distributed Computation with Communication Delays: Asymptotic Performance Analysis
Affiliation:1. Department of Biochemistry, University of Allahabad, Prayagraj, Uttar Pradesh, India;2. Lake Erie College of Osteopathic Medicine, Bradenton, FL, USA;1. Centre for Mobile Cloud Computing Research (C4MCCR), University of Malaya, Kuala Lumpur, Malaysia;2. Faculty of Computer Science and Information Technology, University of Malaya, Kuala Lumpur, Malaysia;3. Department of Computer Science, Federal Urdu University of Arts, Science and Technology, Pakistan;4. Department of Software Engineering, College of Computer and Information Sciences, King Saud University, Riyadh 11543, Saudi Arabia;1. Chuiko Institute of Surface Chemistry, National Academy of Sciences of Ukraine, 17, General Naumov Street, Kyiv 03164, Ukraine;2. Department of Chemistry and Biotechnology, Swedish University of Agricultural Sciences, 75007 Uppsala, Sweden;1. Shenzhen Key Laboratory of Advanced Thin Films and Applications, College of Physics and Energy, Shenzhen University 518060, China;2. Laboratory of Glasses and Ceramics, Institute of Chemical Science UMR CNRS 6226, University of Rennes 1, Rennes 35042, France;3. Advanced Materials Institute, Graduate School at Shenzhen, Tsinghua University, Shenzhen 518055, China;1. Tufts University School of Medicine, Department of Anesthesiology and Pain Medicine, Elizabeth''s Medical Center, Boston, Massachusetts, 02135, USA;2. Harvard–MIT Division of Health Sciences and Technology, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA
Abstract:This paper analyzes the effect of communication delay on the optimal distribution of processing loads in distributed computing networks. The processing load is assumed to satisfy the property of arbitrary divisibility. The objective is to divide and distribute this processing load among various processors in the network in order to minimize the processing time. An asymptotic analysis of the performance of such networks is carried out to obtain a limit on the performance enhancement obtained by using additional processors. The architectures considered are linear and single-level tree configurations. The cases when the processors are equipped with and without front-ends are considered.
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