8通道数字信号时序分析实验装置设计

为了丰富数字逻辑设计实验教学内容，拓展数字电路实验测试设备功能，基于FPGA设计8通道数字信号时序分析装置。该装置自带8路标准测试信号，通过2个按键实现8位触发字的设置，当8路输入信号符合触发条件时，使能片上RAM存储模块实现对8路数字信号的存储。存储器满时使能DA转换，通过生成两路模拟信号送入数字示波器X、Y通道，利用示波器的X-Y显示模式实现8路数字逻辑信号的显示；具备手动光标测试功能，能够通过LED显示光标所对应的8路逻辑信号。该装置解决了数字电路实验过程中依靠示波器无法同时观测多路逻辑信号的问题，同时能够作为一个工程实践案例引导学生基于FPGA进行数字系统设计。

Design of 8 channel digital signal timing analysis experimental installation

In order to enrich the teaching content of digital logic design experiment and expand the function of digital circuit experiment testing equipment, an 8-channel digital signal timing analysis device is designed based on FPGA. The device has 8-channel Standard Test signal, and the 8-bit trigger word is set by two keys. When the 8-channel input signal meets the trigger condition, the on-chip RAM is enabled. The storage module realizes the storage of 8 digital signals; when the memory is full, the DA conversion is enabled; two analog signals are generated and sent to the X and Y channels of the digital oscilloscope; the display of 8 digital logic signals is realized by using the X-Y display mode of the oscilloscope; it has the function of manual cursor test and can display the corresponding 8 logos through the LED cursor. Edit the signal. The device solves the problem that the oscilloscope can not simultaneously observe the multi-channel logic signal in the process of digital circuit experiment. At the same time, it can be used as an engineering practice case to guide students to design the digital system based on FPGA.