A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit |
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| Authors: | Xiao Yan Zhang Yiu-Hing Chan Robert Montoye Leon Sigal Eric Schwarz Michael Kelly |
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| Affiliation: | (1) IBM Corp, 2455 South Rd, Poughkeepsie, NY, USA;(2) IBM T.J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, NY, USA |
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| Abstract: | A power and area efficient 108-bit end-around carry adder is implemented using IBM 65nm SOI technology. The adder is used
for a multiply-add fused (MAF) floating point unit. Careful balance of the adder structure and structure-aware layout techniques
enabled this adder to have a latency of 270ps at power consumption of 20mW with 1V supply. |
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