一种高效的可伸缩分组并行有限域乘法器及VLSI实现

文章提出了基于全1多项式基的可伸缩分组并行有限域乘法器结构，并按照最低位先入和最高位先入的方式分别进行了算法描述，分别称为AOPBLSDM（AOP-Based LSD-first Digital-Serial Multiplier）和AOPBMSDM（AOP-Based MSD-first Digital-Serial Multiplier)。该乘法器的结构规整，适于VLSI实现；同时由于该乘法器具有面积和速度可伸缩度大的特点，因而可以在不同的应用场合下找到最佳的实现方案。理论分析及ASIC综合实现结果均表明，本文所提出的结构在面积和速度上具有一定的优势。

An Efficient Digit-Serial Finite Field Multiplier and Its VLSI Implementation

New implementation of digit-serial finite field multi-pliers based on all-one polynomials is presented by LSB-first and MSB-first styles respectively,named as AOPBLSDM(AOP-Based LSD-first Digital-Serial Multiplier)and AOPBMSDM(AOP-Based MSD-first Digital-Serial Multiplier).The multipli-er is suitable for VLSI implementation due to its regularity,and its scalable characteristic makes it possible to trade off between area and performance in different systems with different re-quirements.Both the analysis and ASIC implementation results indicate that the size and time complexities of our proposed multipliers are lower than those of the previous proposed multi-pliers of the same type.