Fully depleted double-gate MSDRAM cell with additional nonvolatile functionality |
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| Authors: | Ki-Heung Park Maryline Bawedin Jong-Ho Lee Young-Ho Bae Kyoung-Il Na Jung-Hee Lee Sorin Cristoloveanu |
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| Affiliation: | 1. Institute of Microelectronics, Electromagnetism and Photonics (UMR 5130), Grenoble Polytechnic Institute, Minatec, B.P. 257, 38016 Grenoble Cedex 1, France;2. School of EECS Engineering and ISRC (Inter-University Research Center), Seoul National University, Gwanak P.O. Box 34, Seoul 151-600, Republic of Korea;3. Department of Electronics Engineering, Uiduk University, Gyeongju 780-713, Republic of Korea;4. Institute of Electronics IES (UMR 5214), University of Montpellier II, 34095 Montpellier Cedex 5, France;5. School of Electrical Engineering, Kyungpook National University, Daegu 702-701, Republic of Korea |
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| Abstract: | We demonstrate a new fully depleted (FD) double-gate (DG) MSDRAM cell, which features SONOS type storage node at the back-gate (control-gate). This single-transistor cell, based on the meta-stable dip (MSD) hysteresis effect, can also be operated in non-volatile memory (NVM) mode. The NVM functionality is achieved by Fowler–Nordheim tunneling hole injection into the nitride storage node; the injected holes induce a permanent inversion layer in silicon body. The proposed device shows a large current ratio between ‘1’ and ‘0’ states (～103) and a wide memory window (～3 V). The effect of the NVM functionality on the MSD hysteresis was investigated and combined with the effect of the control-gate bias. The SONOS charging can be used for replacing the second gate (i.e. enabling single-gate MSDRAM) or for achieving ‘unified’ memory operation. |
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