Adaptive order reduction scheme for high-order single-bit /spl Delta//spl Sigma/ Modulators

A scheme for achieving adaptive reduction in the order of the loop filter of usual high-order, single-stage, single-bit Delta-Sigma (/spl Delta//spl Sigma/) modulators is proposed in order to improve their performance. The resulting /spl Delta//spl Sigma/ modulators can recover from instability effectively, having also an extended input signal range in comparison to that of the corresponding conventional /spl Delta//spl Sigma/ modulators.