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基于不相交项并行列表技术的FPRM实现
引用本文:王玉花, 王伦耀, 夏银水. 基于不相交项并行列表技术的FPRM实现[J]. 电子与信息学报, 2014, 36(9): 2258-2264. doi: 10.3724/SP.J.1146.2013.01536
作者姓名:王玉花  王伦耀  夏银水
作者单位:宁波大学信息科学与工程学院 宁波315211
基金项目:国家自然科学基金,浙江省自然科学基金,宁波市自然科学基金(2013A610009)资助课题
摘    要:针对传统列表技术在逻辑函数从AND/OR形式转化成固定极性Reed-Muller(FPRM)过程中只能处理小规模电路的不足,该文提出一种基于不相交乘积项的并行列表技术。该技术能有效避免转化算法因逻辑函数输入变量增加引起最小项数量激增而导致效率低下甚至无法工作这种情况。另外,不同于已发表的用于实现大电路的转化算法,待处理的电路结构对该方法的性能影响很小。提出的算法用C语言编程实现,并用MCNC标准电路进行测试。实验结果表明所提算法可以对更大规模电路实现快速FPRM转换,并且算法速度对电路输入个数不敏感,但与待处理逻辑函数的不相交乘积项的数量有关。

关 键 词:数字电路   Reed-Muller (RM)逻辑   固定极性   并行列表技术   逻辑优化
收稿时间:2013-10-10
修稿时间:2014-02-18

FPRM Conversion Using Parallel Tabular Technique with Disjointed Products
Wang Yu-Hua, Wang Lun-Yao, Xia Yin-Shui. FPRM Conversion Using Parallel Tabular Technique with Disjointed Products[J]. Journal of Electronics & Information Technology, 2014, 36(9): 2258-2264. doi: 10.3724/SP.J.1146.2013.01536
Authors:Wang Yu-hua  Wang Lun-yao  Xia Yin-shui
Abstract:With the deficiency of the published tabular techniques based algorithms which can only handle small functions in the conversion from AND/OR forms to the Fixed Polarity Reed-Mull (FPRM) forms, a novel parallel tabular technique using the disjoint products is proposed. By utilizing the disjointed products, the proposed algorithm is able to avoid the rapid increase of the minterms which leads the reported tabular technique based algorithms cannot run efficiently or even out of work. Furthermore, unlike the published algorithm for the large functions conversion, the circuit structure in progress has little effect on the performance of the proposed algorithm. The proposed algorithm is implemented in C language and tested under MCNC benchmarks. The experimental results show that the proposed algorithm can finish the polarity conversion fast for the larger circuits and the speed of the algorithm does not depend on the number of inputs of the circuits but the number of the disjointed products.
Keywords:Digital circuit  Reed-Muller (RM) logic  Fixed polarity  Parallel tabular technique  Logic optimization
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