| 具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器 |
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| 引用本文： | 秦鹏,李金波,康健,李小勇,周健军.具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器[J].半导体学报,2014,35(9):095007-5. |
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| 作者姓名： | 秦鹏 李金波 康健 李小勇 周健军 |
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| 摘 要： | A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.
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| 关 键 词： | 频率合成器 搜索算法 低噪声 自校准 压控振荡器 AFC 电压控制振荡器 相位噪声 |
| 修稿时间： | 4/3/2014 12:00:00 AM |
Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm |
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| Qin Peng,Li Jinbo,Kang Jian,Li Xiaoyong and Zhou Jianjun.Low noise frequency synthesizer with self-calibrated voltage controlled oscillator and accurate AFC algorithm[J].Chinese Journal of Semiconductors,2014,35(9):095007-5. |
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| Authors: | Qin Peng Li Jinbo Kang Jian Li Xiaoyong and Zhou Jianjun |
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| Affiliation: | Centre for Analog/Radio Frequency Integrated Circuits (CARFIC), Shanghai Jiao Tong University, Shanghai 200240, China;Centre for Analog/Radio Frequency Integrated Circuits (CARFIC), Shanghai Jiao Tong University, Shanghai 200240, China;Centre for Analog/Radio Frequency Integrated Circuits (CARFIC), Shanghai Jiao Tong University, Shanghai 200240, China;Centre for Analog/Radio Frequency Integrated Circuits (CARFIC), Shanghai Jiao Tong University, Shanghai 200240, China;Centre for Analog/Radio Frequency Integrated Circuits (CARFIC), Shanghai Jiao Tong University, Shanghai 200240, China |
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| Abstract: | A low noise phase locked loop (PLL) frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator (LO) carriers. Tested 11.5 GHz LO bears a phase noise of -104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm2, including bias circuits and buffers. |
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| Keywords: | 65 nm CMOS self-calibrated VCO accurate AFC search algorithm low noise frequency synthesizer charge pump |
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