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一种SFDR为83.5dB的14位100兆流水线模数转换器
引用本文:赵南,魏琦,杨华中,汪蕙. 一种SFDR为83.5dB的14位100兆流水线模数转换器[J]. 半导体学报, 2014, 35(9): 095009-8
作者姓名:赵南  魏琦  杨华中  汪蕙
基金项目:国家自然科学基金;国家高技术研究发展计划(863计划)
摘    要:This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

关 键 词:CMOS技术  动态范围  ADC  MS  杂散  dB  流水线  非线性模型

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR
Zhao Nan,Wei Qi,Yang Huazhong and Wang Hui. A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR[J]. Chinese Journal of Semiconductors, 2014, 35(9): 095009-8
Authors:Zhao Nan  Wei Qi  Yang Huazhong  Wang Hui
Affiliation:Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China;Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China;Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China;Division of Circuits and Systems, Department of Electronic Engineering, Tsinghua University, Beijing 100084, China
Abstract:pipelined ADC bootstrapped switch gradient error pseudo-random sequence
Keywords:pipelined ADC  bootstrapped switch  gradient error  pseudo-random sequence
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