| 基于Verilog的RISC MCU中断系统的设计与验证 |
| |
| 引用本文： | LING Chao Dong,柯志斌,WANG Jia Xian.基于Verilog的RISC MCU中断系统的设计与验证[J].电子技术应用,2008,34(3). |
| |
| 作者姓名： | LING Chao Dong 柯志斌 WANG Jia Xian |
| |
| 作者单位： | 元顺集成电路设计中心,华侨大学信息学院,福建,泉州,362021;元顺集成电路设计中心,华侨大学信息学院,福建,泉州,362021;元顺集成电路设计中心,华侨大学信息学院,福建,泉州,362021 |
| |
| 基金项目： | 福建省自然科学基金，福建省厦门市科技计划 |
| |
| 摘 要： | 详细论述了4位RISC MCU中断系统的Verilog设计实现过程。该MCU采用PIC两级流水线结构,含4个中断源,2级优先级。最后通过整体的RISC MCU IP核对其中断系统进行完整的程序测试,完成功能与时序的仿真与验证。
|
| 关 键 词： | verilog PIC RISCMCU 仿真 中断 |
The design and verification of RISC MCU's interrupt system based on Verilog |
| |
| LING Chao Dong,KE Zhi Bin,WANG Jia Xian.The design and verification of RISC MCU's interrupt system based on Verilog[J].Application of Electronic Technique,2008,34(3). |
| |
| Authors: | LING Chao Dong KE Zhi Bin WANG Jia Xian |
| |
| Affiliation: | LING Chao Dong,KE Zhi Bin,WANG Jia Xian (Yunshun IC Design Research & Development laboratory,Huaqiao University,Quanzhou 362021,China) |
| |
| Abstract: | The process of design and realization of 4-bit RISC MCU’s interrupt system based on Verilog is illustrated in detail. The MCU adopts two-stage pipeline architecture of PIC, includes four interrupt sources and two priority ranks. Finally, program tests using instructions are carried out through the whole RISC MCU IP core, simulation and verification in function and timing are presened. |
| |
| Keywords: | verilog PIC RISCMCU |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
