A mixed-mode polynomial cellular array processor hardware realization

A mixed-mode cellular array processor is presented in which the processing units (PUs) are coupled with programmable polynomial (linear, quadratic, and cubic) first neighborhood feedback terms. It combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks whereas the integrator is digital, and analog-to-digital and digital-to-analog converters are used to interface between them. A 10-mm/sup 2/, 1.027 million transistor cellular array processor with 2/spl times/72 PUs and 36 layers of memory in each was manufactured using a 0.25-/spl mu/m digital CMOS process. The array processor can perform gray scale Heun's integration of spatial convolutions with linear, quadratic, and cubic activation functions for a 72/spl times/72 data while keeping all input-output operations during processing local. One complete Heun's iteration round takes 166.4 /spl mu/s and the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.