A CMOS 0.25-/spl mu/m continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission

This paper presents a CMOS 0.25-/spl mu/m continuous-time 6-tap FIR filter that is used as a fractionally spaced receiver equalizer for 1-Gb/s data transmission. Each tap of the FIR filter delay line is realized with a second-order low-pass filter. Simulations show that the tap delay can be tuned from 100 ps to 300 ps while keeping a constant group delay within the bandwidth of 2.1 GHz and 800 MHz correspondingly. Experimental results show that the FIR filter can successfully recover a 1-Gb/s differential digital signal that has been transmitted over a 220-inch PCB trace which causes -31.48-dB attenuation at the symbol rate frequency of 1 GHz. The measured bit error rate after equalization is less than 10/sup -12/ over a 750-ps sampling range, compared to a 10/sup -2/ bit-error rate before equalization. Also presented are the measurement results comparing the horizontal and the vertical openings of the signals before and after equalization for PCB traces with different length. The chip dissipates 45 mW from a 2.5-V supply and occupies 0.33/spl times/0.27 mm/sup 2/ in a 0.25-/spl mu/m CMOS process.