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具有应变沟道及EOT 1.2nm高性能栅长22nm CMOS器件
引用本文:徐秋霞,钱鹤,段晓峰,刘海华,王大海,韩郑生,刘明,陈宝钦,李海欧.具有应变沟道及EOT 1.2nm高性能栅长22nm CMOS器件[J].半导体学报,2006,27(13):283-290.
作者姓名:徐秋霞  钱鹤  段晓峰  刘海华  王大海  韩郑生  刘明  陈宝钦  李海欧
作者单位:中国科学院微电子研究所,北京 100029;中国科学院微电子研究所,北京 100029;中国科学院物理研究所,北京 100080;中国科学院物理研究所,北京 100080;中国科学院微电子研究所,北京 100029;中国科学院微电子研究所,北京 100029;中国科学院微电子研究所,北京 100029;中国科学院微电子研究所,北京 100029;中国科学院微电子研究所,北京 100029
摘    要:深入研究了亚30nm CMOS关键工艺技术,特别是提出了一种新的低成本的提高空穴迁移率的技术--Ge预非晶化S/D延伸区诱生沟道应变技术,它使栅长90nm pMOS空穴有效迁移率在0.6MV/cm电场下提高32%. 而且空穴有效迁移率的改善,随器件特征尺寸缩小而增强. 利用零阶劳厄线衍射的大角度会聚束电子衍射分析表明,在沟道区相应的压应变为-3.6%. 在集成技术优化的基础上,研制成功了高性能栅长22nm应变沟道CMOS器件及栅长27nm CMOS 32分频器电路(其中分别嵌入了57级/201级环形振荡器), EOT为1.2nm,具有Ni自对准硅化物.

关 键 词:应变硅沟道  压应力  Ge预非晶化注入  等效氧化层厚度  栅长  CMOS

High Performance Gate Length 22nm CMOS Device withStrained Channel and EOT 1.2nm
Xu Qiuxi,Qian He,Duan Xiaofeng,Liu Haihu,Wang Dahai,Han Zhengsheng,Liu Ming,Chen Baoqin and Li Haiou.High Performance Gate Length 22nm CMOS Device withStrained Channel and EOT 1.2nm[J].Chinese Journal of Semiconductors,2006,27(13):283-290.
Authors:Xu Qiuxi  Qian He  Duan Xiaofeng  Liu Haihu  Wang Dahai  Han Zhengsheng  Liu Ming  Chen Baoqin and Li Haiou
Affiliation:Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029, China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029, China;Institute of Physics,Chinese Academy of Sciences,Beijing 100080,China;Institute of Physics,Chinese Academy of Sciences,Beijing 100080,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029, China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029, China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029, China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029, China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029, China
Abstract:As scaling CMOS device towards sub-30nm gate length,device physics and semiconductor technology will encounter a series of barriers.This paper deeply investigates sub-30nm CMOS key process technologies,especially offers a new low-cost technique for enhancement of hole mobility using strained channel by Ge pre-amorphization implantation (PAI) for S/D extension to overcome the serious short channel effect (SCE) and to improve drive current/off state leakage ratio,which makes 32% hole effective mobility improvement at 0.6MV/cm vertical field for 90nm gate length pMOS.And the hole mobility enhancement strengthens with the scaling down of feature size of the device.The analysis using zero order Laue Zone diffraction on large angle convergent beam electron diffraction (LACBED) in TEM reveal very large compressive strain of -3.6% (gate length 75nm) in the channel region induced by Ge PAI for S/D extension.Based on the optimum of integration technology,high performance gate length 22nm CMOS devices and gate length 27nm CMOS 32 frequency dividers embedded with 57 stage/201 stage CMOS ring oscillator with strained channel are fabricated successfully with EOT 1.2nm and Ni-SALICIDE.
Keywords:strained channel  compressive stress  Ge PAI  EOT  gate length  CMOS
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