Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO₂ gives the best results for low power and high-speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n-CNTFET and varied for p-CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from ?27 to 127°C. The stability of the proposed SRAM cell is calculated using N-curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.