Capacitor placement for switching noise reduction using genetic algorithms and distributed computing

This work investigates capacitor placement on a printed circuit board (PCB) to reduce the effect of simultaneous switching noise as a genetic algorithm (GA) search problem. The solution process makes use of distributed computing resources available on a local area network in order to solve larger problems more efficiently. The objective is to determine the number of added capacitors with minimum cost, and their position on the PCB, while keeping the maximum voltage deviation within some specified noise margin. The presence of capacitors at the selected positions is represented by a stream of zeros and ones, which is interpreted as a genotype. At each generation, the GA assesses the fitness function of a population of genotypes using linear transient circuit analysis, which involves a single matrix inversion, by determining the maximum voltage dip given the capacitor locations. For large systems, the fitness calculations are divided among several processors according to a simple distributed computing algorithm.