减少数字集成电路测试时间的扫描链配置

研究了通过扫描链配置缩短数字集成电路测试时间问题。利用图论中的极大独立集来描述被测电路主输入的结构无关性。通过结构无关主输入共用扫描寄存器,以缩短扫描链长度进而减少扫描测试时间。提出了利用被测电路主输出可控性来分配一主输入至某一共用扫描寄存器的主输入组,直至形成一个极大组,这改进了利用被测电路测试集信息处理同样问题的方法1]。还分析了在多输出有扇出电路中插入内置扫描单元,以增大结构无关输入的实现方法。对国际标准电路的实验证明了该方法是减少数字集成电路扫描测试时间的一条有效途径。

On Scan Chains Configuration for Reducing Test Time of Digital Integrated Circuits

Shortening test application time of digital integrated circuits by scan chain configuration is researched. Maximum independent set in graph theory is applied to describe the structural independencies of primitive inputs of circuits under test. By sharing scan registers among primitive inputs with structural independency, the length of scan chains is reduced and as a result scan test time is shortened accordingly. The controllability of primitive output of circuits under test is used as a formula to assign a primitive input into a group, until a maximum group, which shares the same scan register, is established. This method presented improved the technique reported in 1], which solve similar question above by aid of test set information of circuits under test. To multiple output circuits with fanouts, the implementation of inserting built|in scan cells to enlarge structurally independent inputs is analyzed also. Experimental results on international benchmark circuits proved the method presented is one of effective means aiming at reducing scan test application time of digital integrated circuits.