时钟数据恢复电路中相位插值器的分析和设计

分析了应用于时钟恢复电路中的相位插值器.为相位插值器建立了数学模型并基于模型对相位插值器在数学域进行了详细的分析.分析结果表明相位插值器输出时钟的相位和幅度强烈地依赖于插值器输入时钟间的相位差,同时提出一种新的编码方法来补偿相位的非线性.考虑到实际电路中寄生效应,文章同样在电路域中对相位插值器进行了详细分析.通过建立电路模型得到RC时间常数和输入时钟间的相差的关系,得到了它对相位插值器线性的影响.在设计中通过在PI的输入增加可控RC的输入缓冲器来调整输入时钟沿的快慢,从而降低了这种影响.最后利用分析得到的结论,使用90nm CMOS工艺设计并制造了一个相位插值器.它的供电电压为1.2V,功耗为1mw,工作范围从1GHz到5GHz.测试结果表明,输出相位单调并具有良好的线性度,验证了分析的正确性.

Analysis and Design of a Phase Interpolator for Clock and Data Recovery

In this paper,a detailed analysis of a phase interpolator for clock recovery is presented.A mathematical model is setup for the phase interpolator and we perform a precise analysis using this model.The result shows that the output amplitude and linearity of phase interpolator is primarily related to the difference between the two input phases.A new encoding pattern is given to solve this problem.Analysis in the circuit domain was also undertaken.The simulation results show that the relation between RC time-constant and time difference of input clocks affects the linearity of the phase interpolator.To alleviate this undesired effect,two adjustable-RC buffers are added at the input of the PI.Finally,a 90nm CMOS phase interpolator,which can work in the frequency from 1GHz to 5GHz,is proposed.The power dissipation of the phase interpolator is 1mW with a 1.2V power supply.Experiment results show that the phase interpolator has a monotone output phase and good linearity.