An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor |
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Authors: | Shuenn-Shyang Wang Chien-Sung Li |
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Affiliation: | (1) Department of Electrical Engineering, Tatung University, 40 Sec. 3, Chungshan N. Road, Taipei, 103, Taiwan, Republic of China |
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Abstract: | Fast Fourier transform (FFT) plays an important role in the orthogonal frequency division multiplexing (OFDM) communication systems. In this paper, we propose an area-efficient design of variable-length FFT processor which can perform various FFT lengths of 512/1,024/2,048/4,096/8,192 points used in OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). To reduce computational complexity and chip area, we develop a new variable-length FFT architecture by devising a mixed-radix algorithm that consist of radix-2, radix-22 and radix-2/4/8 algorithms and optimizing the realization by substructure sharing. Based on this architecture, an area-efficient design of variable-length FFT processor is presented. By synthesized using the UMC 0.18 μm process, the area of the processor is 2.9 mm2 and the 8,192-point FFT can be performed correctly up to 50 MHz with power consumption 823 mW under a 1.8 V supply voltage. |
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Keywords: | variable length FFT Fast Fourier Transform OFDM substructure sharing |
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