Noise in CMOS Voltage Controlled Relaxation Oscillators

A low-noise voltage controlled relaxation oscillator (VCO) has been fabricated in a 2 micron CMOS process. The VCO uses a grounded external timing capacitor and a bypassed latch. A theoretical analysis is presented showing that the VCOs output phase noise is dominated by the undersampling of circuit noise arising principally from the comparators. A minor correction to equation (21) of Abidi and Meyer in [1] is also derived. The VCO design was modified to allow a comparison between two different comparator architectures whilst sharing a common VCO core of current sources, timing capacitor and latch. Spectrum analyzer measurements are presented which confirm the theoretical predictions and show that high frequency signals are aliassed down to appear as noise sidebands about the carrier frequency. The oscillator's phase noise was measured as –70 dBc/Hz at a 20 kHz offset when oscillating at 1.1 MHz.