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Dynamic thread mapping of shared memory applications by exploiting cache coherence protocols
Authors:Eduardo HM Cruz  Matthias Diener  Marco AZ Alves  Philippe OA Navaux
Affiliation:Informatics Institute, Federal University of Rio Grande do Sul (UFRGS), Av. Bento Gonçalves, 9500, Campus do Vale, Bloco IV, Lab 201-67, Postal Code 91501-970, Porto Alegre, RS, Brazil
Abstract:In current computer architectures, the communication performance between threads varies depending on the memory hierarchy. This performance difference must be considered when mapping parallel applications to processor cores. In parallel applications based on the shared memory paradigm, the communication is difficult to detect because it is implicit. Furthermore, dynamic mapping introduces several challenges, since it needs to find a suitable mapping and migrate the threads with a low overhead during the execution of the application. We propose a mechanism to detect the communication pattern of shared memory applications by monitoring cache coherence protocols. We also propose heuristics that, combined with our communication detection mechanism, allow the mapping to be performed dynamically by the operating system. Experiments with the NAS Parallel Benchmarks showed a reduction of up to 13.9% of the execution time, 30.5% of the cache misses and 39.4% of the number of invalidation messages.
Keywords:Thread mapping  Cache coherence protocols  Parallel applications  Shared memory  Thread communication  Communication pattern
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