Technology and design challenges of MOS VLSI

The past decade of MOS technology has been characterized by the scaling of Si-gate LOCOS NMOS to ever smaller geometries. However, NMOS circuits with 1 /spl mu/m geometries will not be achieved by continued direct scaling of this structure. Major changes will be required in the 1-2 /spl mu/m range in terms of: 1) process and structure enhancements that will be required to realize the performance advantages predicted by scaling, and 2) new physical phenomena that will become important in determining MOSFET behavior. The 1-2 /spl mu/m range of NMOS technology is referred to as the `1.25 /spl mu/m discontinuity'. Both aspects of this discontinuity are explored, and some projections for MOS are made for the next decade.