基于FPGA的快速樱桃缺陷检测与识别系统设计

为使樱桃缺陷检测与识别系统满足实时性的要求,提出以卷积神经网络模型为基础,使用SDSoC开发平台,完成FPGA对樱桃缺陷进行快速检测与识别系统的设计。通过优化数据传输,复用网络模型中通用矩阵乘法函数(GEMM)和对卷积操作进行并行化设计,实现PL端硬件加速。利用SDSoC平台,在PS端使用高级语言映射卷积神经网络模型,在实现所需性能的同时大量节省了开发时间。结果表明,与纯软件方式相比,基于Zynq7020硬件开发平台,速度提高了2.19倍以上,与CPU平台相当。

Design of fast cherry defect detection and recognition system based on FPGA

To make the cherry defect detection and identification system meet the real-time requirements, it was proposed to use the convolutional neural network model as the basis and used the SDSoC development platform to complete the design of FPGA for rapid detection and identification of cherry defects. By optimizing data transmission, multiplexing the general matrix multiplication function (GEMM) in the network model and parallelizing the design of the convolution operation, PL-side hardware acceleration was realized. Using the SDSoC platform, a high-level language mapping convolutional neural network model was used on the PS-side, which saved a lot of development time while achieving the required performance. The results showed that, compared with the pure software method, the speed based on the Zynq7020 hardware development platform had increased by more than 2.19 times. Compared with the CPU platform, the speed was almost the same.