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Expressive program verification via structured specifications
Authors:Cristian Gherghina  Cristina David  Shengchao Qin  Wei-Ngan Chin
Affiliation:1. Singapore University of Technology and Design, Singapore, Singapore
2. University of Oxford, Oxford, UK
3. Shenzhen University, Shenzhen, China
4. Teesside University, Middlesbrough, UK
5. National University of Singapore, Singapore, Singapore
Abstract:Conventional specifications typically have a flat structure that is based primarily on the underlying logic. Such specifications lack structures that could provide better guidance to the verification process. In this work, we propose to add three new structures to a specification framework for separation logic to achieve a more precise and better guided verification for pointer-based programs. The newly introduced structures empower users with more control over the verification process in the following ways: (1) case analysis can be invoked to take advantage of disjointedness conditions in the logic, (2) early, as opposed to late, instantiation can minimise the use of existential quantification and (3) novel formulae structuring can provide better reuse of the verification process. Initial experiments have shown that structured specifications can lead to more precise verification without incurring any performance overhead. To support our proposal, we shall illustrate the usage of structured specifications in the context of proving termination and we will briefly outline the impact of our proposal on a recent development focussed on verifying the FreeRTOS scheduler Ferreira et al. (Int. J. Softw. Tools Technol. Trans. 2014).
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