一种ADC中采用的开关电容比较器的设计

文章介绍了一款模数转换器中采用高精度开关电容结构的比较器电路的设计。该电路采用3阶放大结构，具有低失调、低功耗、精度高、易于扩展等优点。文中详细介绍了开关电容比较器的基本工作原理，分析了电路误差的产生机理，在此基础上提出了为减小失调和误差、进一步改善电路性能而采取的抑制开关电容比较器电荷注入和时钟馈通效应提高精度的具体措施。电路设计基于中微晶圆0．6μm N-WELL DPDM CMOS工艺。并使用HSPICE软件进行仿真，整个电路通过流片验证，电路参数达到设计指标，满足使用要求。

A Switch Capacitor Voltage Comparator for ADC

This paper introduced a kind of switch capacitor voltage comparator for ADC. The comparator adopts three stages amplifiers,the structure has the characteristics with low offset,good precision,easily expanded and low power dissipation .This paper analysis the theory of the comparator and the method of how to decrease the channel charge injection and clock feedthrough,the method can effectively improved the performance of switch capacitor.The circuit fabricated in KI 0.6μm N-WELL DPDM CMOS process and emulated by HSPICE, the entire circuit have verified by wafer,the parameters of the circuit meet the designing goal,the circuit reach the requirement of using.