Silicon-on-insulator nanotransistors with two independent gates

The results of numerical simulation of electrical characteristics of silicon-on-insulator MOSFET nanotransistors with two independent gates are reported. The cases of grounded and floating bases with the surface recombination of charge carriers either disregarded or taken into account are considered. It is shown that, at specified design parameters (gate length 50–100 nm, thickness of silicon layer 25–50 nm), one can vary the transistor’s threshold voltage by 0.45 V, reduce the transistor current in the off state by seven orders of magnitude, and decrease the subthreshold slope of the gate characteristics to 60 mV/decade by varying the voltage applied to the second gate. Suppression of the short-channel effects in the transistors under consideration depends on a number of parameters (listed in order of decreasing effect): the gate material, the lifetime of charge carriers (for floating or grounded base), the thickness of the top silicon layer, the voltage applied to the additional gate, and the channel length.