金-硅共晶焊工艺应用研究

在混合集成电路中,对芯片的贴装多采用导电胶粘接工艺,但是由于其电阻率大、导热系数低和损耗大,难以满足各方面的要求;另一方面导电胶随着时间的推移会产生性能退化,难以满足产品30年以上长期可靠性的要求。而对于背面未制作任何金属化或仅仅制作了单层金的硅芯片又难以采用常规的焊接工艺进行贴装。介绍了一种硅芯片的贴装工艺金-硅共晶焊工艺,并对两种主要失效模式和工艺实施过程中影响质量的因素以及解决办法进行了论述。

Applied Study of Au-Si Eutectic Bonding Process

In hybrid integrated circuits,conductive adhesive bonding technology is widely adopted by die placement.However,this process can not meet the requirement due to its high electronic resistance,low thermal conductivity and high depletion.In addition,performance degradation of conductive adhesive will appear over time,which makes the products difficultly to meet the requirement of long term reliability over 30 years.For the silicon chip no metals or with monolayer gold on back side,it is usually hard to adopt conventional soldering process for die placement.Introduce one process for silicon chip placement,AuSi eutectic bonding process,its two main failure modes and influence factors to quality in the technical process together with relevant solutions are discussed.